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The TAU is controlled through three supervisor-level SPRs, accessed through the mtspr/
mfspr instructions. Two of the SPRs (THRMI and THRM2) provide temperature threshold
values that can be compared to the junction temperature value, and control bits that enable
comparison and thermal interrupt generation. The third SPR (THRM3) provides a TAU
enable bit and a sample interval timer. Note that all the bits in THRMl, THRM2, and
THRM3 are cleared to 0 during a hard reset, and the TAU remains idle and in a low-power
state until configured and enabled.
The bit fields in the THRMI and THRM2 SPRs are described in Table 10-2.
Table 10-2. THRM1 and THRM2 Bit Field Settings
Bits
Field
Description
0
TIN
Thermal management interrupt bit. Read only. This bit is set if the thermal sensor output
crosses the threshold specified in the SPR. The state of this bit is valid only if TIV is set. The
interpretation of the TIN bit is controlled by the TID bit.
1
TIV
Thermal management interrupt valid. Read only. This bit is set by the thermal assist logic to
indicate that the thermal management interrupt (TIN) state is valid.
2-8
Threshold
Threshold value that the output of the thermal sensor is compared to. The threshold range is
between 0
0
and 127" C, and each bit represents 1
0
C. Note that this is not the resolution of
the thermal sensor.
9-28
-
Reserved. System software should clear these bits to O.
29
TID
Thermal management interrupt direction bit. Selects the result of the temperature
comparison to set TIN. If TID is cleared to 0, TIN is set and an interrupt occurs if the junction
temperature exceeds the threshold.
If
TID is set to 1, TIN is set and an interrupt is indicated
if the junction temperature is below the threshold.
30
TIE
Thermal management interrupt enable. Enables assertion of the thermal management
interrupt Signal. The thermal management interrupt is maskable by the MSR[EE] bit. If TIE is
cleared to 0 and THRMn is valid, the TIN bit records the status of the junction temperature
vs. threshold comparison without asserting an interrupt signal. This feature allows system
software to make a successive approximation to estimate the junction temperature.
31
V
SPR valid bit. This bit is set to indicate that the SPR contains a valid threshold, TID, and TIE
controls bits. Setting THRM1/2[V] and THRM3[E] to 1 enables operation of the thermal
sensor.
The bit fields in the THRM3 SPR are described in Table 10-3.
Table 10-3. THRM3 Bit Field Settings
Bits
Name
Description
0-17
-
Reserved for future use. System software should clear these bits to O.
18-30
SITV
Sample interval timer value. Number of elapsed processor clock cycles before a junction
temperature vs. threshold comparison result is sampled for TIN bit setting and interrupt
generation. This is necessary due to the thermal sensor, DAC, and the analog comparator
settling time being greater than the processor cycle time. The value should be configured to
allow a sampling interval of 20 microseconds.
31
E
Enables the thermal sensor compare operation if either THRMl [V] or THRM2[V] is set to 1.
Chapter 10. Power and Thermal Management
10-7
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