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Figure 8-18 shows data-delay controls in a single-beat write operation. Note that all
bidirectional signals are three-stated between bus tenures. Data transfers are delayed in the
following ways:
• The TA signal is held negated to insert wait states in clocks 3 and 4.
•
In clock 6, DBG is held negated, delaying the start of the data tenure.
The last access is not delayed (DRTRY is valid only for read operations).
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2
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3
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4
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6
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BR
~
\'--......---;-J'
\'---;---;-J'
BG
n
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LLJ
: LLJ
! LLJ
A[Q-31]
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TT[O-4]
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AACK
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ARTRY:
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DBB:
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D[Q-63]
~: -+-+--C:=~o~ut==:=}-+--+-~--;'--:
~~~~rt--!L~~~~~~-L~~
URTRY!
TEA:
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Figure 8-18. Single-Beat Writes Showing Data Delay Controls
Chapter 8. System Interface Operation
8-31
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