Memory Management - Motorola MPC750 User Manual

Table
1-5.
Exceptions and Conditions (Continued)
Exception Type
Vector Offset
Causing Conditions
(hex)
Alignment 00600
.
A floating-point load/store, stmw, stwcx, Imw, Iwarx, eciwx or ecowx
instruction operand is not word-aligned.
.
A multiple/string load/store operation is attempted in little-end ian mode .
The operand of dcbz is in memory that is write-through-required or
caching-inhibited or the cache is disabled
Program 00700 As defined by the PowerPC architecture.
Floating-point
00800 As defined by the PowerPC architecture.
unavailable
Decrementer 00900 As defined by the PowerPC architecture, when the most significant bit of the
DEC register changes from 0 to 1 and MSR[EE]
=
1.
Reserved
OOAOO-OOBFF
-
System call OOCOO Execution of the System Call (sc) instruction.
Trace 00000 MSR[SE]
=
1 or a branch instruction completes and MSR[BE]
=
1. Unlike the
architecture definition, isync does not cause a trace exception
Reserved
OOEOO The MPC750 does not generate an exception to this
vector.
Other PowerPC
processors may use this
vector
for floating-point assist exceptions.
Reserved
OOE 1 O-oOEFF
-
Performance monitorl OOFOO The limit specified in a PMC register is reached and MMCRO[ENINT]
=
1
Instruction address 01300 IABR[0-29] matches EA[0-29] of the next instruction to complete, IABR[TE]
breakpoint
1
matches MSR[IR], and IABR[BE]
=
1.
System management
interrupt
1
01400 MSR[EE]
=
1 and SMI is asserted.
Reserved
01500-016FF
-
Thermal management 01700 Thermal management is enabled, the junction temperature exceeds the
interrupt
1
threshold specified in THRM1 or THRM2, and MSR[EE]
=
1.
Reserved
01800-02FFF
-
Note:
1
MPC750-specific
1.8 Memory Management
The following subsections describe the memory management features of the PowerPC
architecture, and the MPC750 implementation, respectively. A detailed description of the
MPC750 MMU implementation is provided in Chapter 5, "Memory Management."
1-32 MPC750 RISC Microprocessor User's Manual