Signals - Motorola MPC750 User Manual

Address Arbitration
Address Start
Address Transfer
Transfer Attribute
Address Termination
Clocks
System Status
MPC750
I I
Data Arbitration
Data Transfer
Data Termination
L2 Cache Clock/Cantrall
L2 Cache Address/Data l
Processor Status/Control
Test and Control
VDD VDD (I/O)
1
Not supported in the
MPC740
Figure 1-3. System Interface
The system interface supports address pipelining, which allows the address tenure of one
transaction to overlap the data tenure of another. The extent of the pipelining depends on
external arbitration and control circuitry. Similarly, the MPC750 supports split-bus
transactions for systems with multiple potential bus masters-one device can have
mastership of the address bus while another has mastership of the data bus. Allowing
multiple bus transactions to occur simultaneously increases the available bus bandwidth for
other activity.
The MPC750's clocking structure supports a wide range processor-to-bus clock ratios.
1.2.7 Signals
The MPC750's signals are grouped as follows:
• Address arbitration signals-The MPC750 uses these signals to arbitrate for address
bus mastership.
• Address start signals-These signals indicate that a bus master has begun a
transaction on the address bus.
• Address transfer signals-These signals include the address bus and address parity
signals. They are used to transfer the address and to ensure the integrity of the
transfer.
• Transfer attribute signals-These signals provide information about the type of
transfer, such as the transfer size and whether the transaction is bursted, write-
through, or caching-inhibited.
• Address termination signals-These signals are used to acknowledge the end of the
address phase of the transaction. They also indicate whether a condition exists that
requires the address phase to be repeated.
• Data arbitration signals-The MPC750 uses these signals to arbitrate for data bus
mastership.
• Data transfer signals-These signals, which consist of the data bus and data parity
signals, are used to transfer the data and to ensure the integrity of the transfer.
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