Optional External Control Instructions - Motorola MPC750 User Manual

Table 2-53. User-Level Cache Instructions (Continued)
Name
Mnemonic Syntax Implementation Notes
Data Cache Block debst rA,rB The EA is computed, translated, and checked for protection violations,
Store
·
For cache hits with the tag marked E, no further action is taken.
·
For cache hits with the tag marked M, the cache block is written back
to memory and marked E.
A debst is not broadcast unless HIOO[ABE]
=
1 regardless of WIMG
settings. The instruction acts like a load with respect to address translation
and memory protection. It executes regardless of whether the cache is
disabled or locked.
The exception priorities (from highest to lowest) for debs! are as follows:
1 BAT protection violation-OSI exception
2 TLB protection violation-OS I exception
Data Cache Block debt rA,rB The EA is computed, translated, and checked for protection violations.
Flush
·
For cache hits with the tag marked M, the cache block is written back
to memory and the cache entry is invalidated.
·
For cache hits with the tag marked E, the entry is invalidated.
·
For cache misses, no further action is taken.
A debt is not broadcast unless HIOO[ABE]
=
1 regardless of WIMG
settings. The instruction acts like a load with respect to address translation
and memory protection. It executes regardless of whether the cache is
disabled or locked.
The exception priorities (from highest to lowest) for debt are as follows:
1 BAT protection violation-OS I exception
2 TLB protection violation-OS I exception
Instruction Cache iebi rA,rB This instruction performs a
virtual
lookup into the instruction cache (index
Block Invalidate only). The address is not translated, so it cannot cause an exception. All
ways of a selected set are invalidated regardless of whether the cache is
disabled or locked. The MPC750
never
broadcasts iebi onto the 60x bus.
Note:
1
A program that uses debt and dcbtst instructions improperly performs less efficiently. To improve
performance, HIDO[NOOPTI] may be set, which causes debt and dcbtst to be no-oped at the
cache. They do not cause bus activity and cause only a 1-clock execution latency. The default
state of this bit is zero which enables the use of these instructions.
2.3.5.4 Optional External Control Instructions
The PowerPC architecture defines an optional external control feature that, if implemented,
is supported by the two external control instructions, eciwx and ecowx. These instructions
allow a user-level program to communicate with a special-purpose device. These
instructions are provided and are summarized in Table 2-54.
Table 2-54. External Control Instructions
Name Mnemonic Syntax Implementation Notes
External eeiwx rO,rA,rB A transfer size of 4 bytes is implied; the TBST and TSIZ[O-2] signals are
Control In redefined to specify the Resource 10 (RID), copied from bits EAR[28-31]. For
Word Indexed these operations, TBST carries the EAR[28] data. Misaligned operands for
External rS,rA,rB
these instructions cause an alignment exception. AddreSSing a location
eeowx
where SR[T]
=
1 causes a OSI exception. " MSR[OR]
=
0 a programming
Control Out
error occurs and the phYSical address on the bus is undefined.
Word Indexed
Note: These instructions are optional to the PowerPC architecture.
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MPC750 RISC Microprocessor User's Manual