Motorola MPC750 User Manual page 39

Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
MSR Machine state register
NaN Not a number
No-op No operation
OEA Operating environment architecture
PIO Processor identification tag
PLL Phase-locked loop
PLRU Pseudo least recently used
PMCn Performance monitor counter registers
POR Power-on reset
POWER Performance Optimized with Enhanced RISC architecture
PTE
Page table entry
PTEG Page table entry group
PVR Processor version register
RAW Read-after-write
RISC
Reduced instruction set computing
RTL Register transfer language
RWITM
Read with intent to modify
RWNITM Read with no intent to modify
SDA
Sampled data address register
SDR1 Register that specifies the page table base address for virtual-to-physical address translation
SIA Sampled instruction address register
SPR Special-purpose register
SRn
Segment register
SRU System register unit
SRRO Machine status save/restore register 0
SRR1 Machine status savelrestore register 1
SRU
System register unit
TAU Thermal management assist unit
TB Time base facility
TBL Time base lower register
TBU Time base upper register
THRMn Thermal management registers
xxxvi MPC750 RISC Microprocessor User's Manual