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3.5 Cache Operations
This section describes the MPC750 cache operations.
3.5.1 Cache Block ReplacementlCastout Operations
Both the instruction and data cache use a pseudo least-recently-used (PLRU) replacement
algorithm when a new block needs to be placed in the cache. When the data to be replaced
is in the modified (M) state, that data is written into a castout buffer while the missed data
is being accessed on the bus. When the load completes, the MPC750 then pushes the
replaced cache block from the castout buffer to the L2 cache (if L2 is enabled) or to main
memory (if L2 is disabled).
The replacement logic first checks to see if there are any invalid blocks in the set and
chooses the lowest-order, invalid block (L[O-7]) as the replacement target. If all eight
blocks in the set are valid, the PLRU algorithm is used to determine which block should be
replaced. The PLRU algorithm is shown in Figure 3-5.
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MPC750 RISC Microprocessor User's Manual
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