Reset Settings - Motorola MPC750 User Manual

2.1.6 Reset Settings
Table 2-19 shows the state of the registers and other resources after a hard reset and before
the first instruction is fetched from address OxFFFO_OlOO (the system reset exception
vector).
Table 2-19. Settings Caused by Hard Reset (Used at Power-On)
Resource Setting Resource
Setting
BATs Undefined MSR
OxOOOO_0040 (only IP set)
Caches (L 1 IL2)* Invalidated and disabled PMCn Undefined
CR Undefined PVR ROM value
CTR
Undefined Reservation address Undefined
DABR Breakpoint is disabled. Address is undefined. Reservation flag Cleared
DAR OxOOOO_OOOO SDR1 OxOOOO_OOOO
DEC OxFFFFJFFF SIA
OxOOOO_OOOO
DSISR OxOOOO_OOOO SPRGO-SPGR3 OxOOOO_OOOO
EAR OxOOOO_OOOO SRs Undefined
FPR Undefined SRRO
OxOOOO_OOOO
FPSCR
OxOOOO_OOOO SRR1 OxOOOO_OOOO
GPR Undefined TBU andTBL
OxOOOO_OOOO
HIDO OxOOOO_OOOO
THRM1-THRM3 OxOOOO_OOOO
HID1 OxOOOO_OOOO TLB Undefined
IABR OxOOOO_OOOO (Breakpoint is disabled.) UMMCRn OxOOOO_OOOO
ICTC OxOOOO_OOOO UPMCn
OxOOOO_OOOO
L2CR OxOOOO_OOOO USIA OxOOOO_OOOO
LR OxOOOO_OOOO XER OxOOOO_OOOO
MMCRn
OxOOOO_OOOO
*
The processor automatically begins operations by issuing an instruction fetch. Because caching is inhibited at
start-up, this generates a single-beat load operation on the bus.
Chapter 2. MPC750 Processor Programming Model
2-27