Motorola MPC750 User Manual page 11

Paragraph
Number
4.4
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
4.5.13
4.5.14
4.5.15
4.5.16
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.6.1
5.1.6.2
5.1.7
5.1.8
5.2
5.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
viii
CONTENTS
Title
Page
Number
Process Switching .............................................................................................. .4-12
Exception Definitions ........................................................................................ .4-12
System Reset Exception (OxOOl00) .............................................................. ..4-13
Machine Check Exception (Ox00200) ........................................................... .4-14
Machine Check Exception Enabled (MSR[ME]
=
1) ............................... .4-16
Checkstop State (MSR[ME]
=
0) .............................................................. .4-16
DSI Exception (Ox00300) .............................................................................. .4-17
lSI Exception (Ox00400) ............................................................................... .4-17
External Interrupt Exception (Ox00500) ....................................................... ..4-17
Alignment Exception (Ox00600) ............. , ..................................................... .4-18
Program Exception (Ox00700) ...................................................................... .4-18
Floating-Point Unavailable Exception (Ox00800) ......................................... .4-19
Decrementer Exception (Ox00900) ................................................................ .4-19
System Call Exception (OxOOCOO) ............................................................... ..4-19
Trace Exception (OxOODOO) .......................................................................... .4-19
Floating-Point Assist Exception (OxOOEOO) .................................................. .4-20
Performance Monitor Interrupt (OxOOFOO) .................................................... .4-20
Instruction Address Breakpoint Exception (Ox01300) .................................. .4-21
System Management Interrupt (Ox01400) ..................................................... .4-22
Thermal Management Interrupt Exception (Ox01700) .................................. .4-24
Chapter 5
Memory Management
MMU Overview ................................................................................................... 5-2
Memory Addressing ......................................................................................... 5-4
MMU Organization .......................................................................................... 5-4
Address Translation Mechanisms ....................... , ..................... '" ..................... 5-9
Memory Protection Facilities ......................................................................... 5-11
Page History Information ............................................................................... 5-12
General Flow ofMMU Address Translation ................................................. .5-12
Real Addressing Mode and Block Address Translation Selection ............. 5-12
Page Address Translation Selection ........................................................... 5-14
MMU Exceptions Summary ........................................................................... 5-16
MMU Instructions and Register Summary .................................................... .5-18
Real Addressing Mode ....................................................................................... 5-20
Block Address Translation ................................................................................ .5-21
Memory Segment Model .................................................................................... 5-21
Page History Recording .................................................................................. 5-21
Referenced Bit ............................................................................................ 5-22
Changed Bit ................................................................................................ 5-23
Scenarios for Referenced and Changed Bit Recording .............................. 5-23
MPC750 RISC Microprocessor User's Manual