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Table 3-4. Bus Operations Caused by Cache Control Instructions (WIM = 001)
Instruction
Current
Next Cache State
Bus Operation
Comment
Cache State
dcbst
M
E
Write with kill
Block is pushed
dcbz
I
M
Write with kill
-
dcbz
E,M
M
Kill block
Writes over modified data
dcbt
I
E
Read-with-intent-t
Fetched cache block is
o-modify
stored in the cache
dcbt
E,M
No change
None
-
dcbtst
I
E
Read-with-intent-t
Fetched cache block is
o-modify
stored in the cache
dcbtst
E,M
No change
None
-
For additional details about the specific bus operations performed by the MPC750, see
Chapter 8, "System Interface Operation."
3.6.3
Snooping
The MPC750 maintains data cache coherency in hardware by coordinating activity between
the data cache, the bus interface logic, the L2 cache, and the memory system. The MPC750
has a copy-back cache which relies on bus snooping to maintain cache coherency with other
caches in the system. For the MPC750, the coherency size of the bus is the size of a cache
block, 32 bytes. This means that any bus transactions that cross an aligned 32-byte
boundary must present a new address onto the bus at that boundary for proper snoop
operation by the MPC750, or they must operate noncoherently with respect to the MPC750.
As bus operations are performed on the bus by other bus masters, the MPC750 bus
snooping logic monitors the addresses and transfer attributes that are referenced. The
MPC750 snoops the bus transactions during the cycle that TS is asserted for any of the
following qualified snoop conditions:
•
The global signal (GBL) is asserted indicating that coherency enforcement is
required.
•
A reservation is currently active in the MPC750 as the result of an lwarx instruction,
and the transfer type attributes (TT[O-4]) indicate a write or kill operation. These
transactions are snooped regardless of whether GBL is asserted to support
reservations in the MEl cache protocol.
The state of ABB is not sampled to determine a qualified snoop condition. All transactions
snooped by the MPC750 are checked for correct address bus parity. Every assertion of TS
detected by the MPC750 (whether snooped or not) must be followed by an accompanying
assertion of AACK.
Chapter 3. L 1 Instruction and Data Cache Operation
3-25
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