Mmu Exceptions Summary - Motorola MPC750 User Manual

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If SR[T] = 0, page address translation is selected. The information in the segment descriptor
is then used to generate the 52-bit virtual address. The virtual address is then used to
identify the page address translation information (stored as page table entries (PTEs) in a
page table in memory). For increased performance, the MPC750 has two on-chip TLBs to
cache recently-used translations on-chip.
If an access hits in the appropriate TLB, page translation succeeds and the physical address
bits are forwarded to the memory subsystem. If the required translation is not resident, the
MMU performs a search of the page table. If the required PTE is found, a TLB entry is
allocated and the page translation is attempted again. This time, the TLB is guaranteed to
hit. When the translation is located, the access is qualified with the appropriate protection
bits. If the access causes a protection violation, either an lSI or DSI exception is generated.
If the PTE is not found by the table search operation, a page fault condition exists, and an
lSI or DSI exception occurs so software can handle the page fault.
5.1.7 MMU Exceptions Summary
To complete any memory access, the effective address must be translated to a physical
address. As specified by the architecture, an MMU exception condition occurs if this
translation fails for one of the following reasons:
Page fault-there is no valid entry in the page table for the page specified by the
effective address (and segment descriptor) and there is no valid BAT translation.
An address translation is found but the access is not allowed by the memory
protection mechanism.
The translation exception conditions defined by the OEA for 32-bit implementations cause
either the lSI or the DSI exception to be taken as shown in Table 5-3.
The state saved by the processor for each of these exceptions contains information that
identifies the address of the failing instruction. Refer to Chapter 4, "Exceptions," for a more
detailed description of exception processing.
5-16
MPC750 RISC Microprocessor User's Manual

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