Table of Contents
Advertisement
Figure 8-17 shows three ways to delay single-beat reads showing data-delay controls:
• The TA signal can remain negated to insert wait states in clock cycles 3 and 4.
•
For the second access,
I5BG
could have been asserted in clock cycle 6.
•
In the third access, DRTRY is asserted in clock cycle 11 to flush the previous data.
Note that all bidirectional signals are three-stated between bus tenures. The pipelining
shown in Figure 8-17 can occur if the second access is not another load (for example, an
instruction fetch).
2
3
I
4
5
6
7 I 8
9
I
10
11
12
13
I
14
I
I
I
I
1
1
I
1
BRI~
1
CV
1
C0
I
1
BG
~
Ai?!o
,'>::'01 :
/\i;;;I?o\ :
Ail,oio(i<;dW
ABB I
\
r--I--,
r---+---.
jr--+---+--;
I
1
'---I.------r-'/
i'
I
/
i
''---;-1--;-'
TS::~
:~
:~
A[0-31]1
1
CPU A
)----+--{
CPU A
~
CPU A
I
I
1
1
1
1
TT[O-4] 1
1
Read)--+--{
Read
>-+--<
Read
1
1
1
1
1
1
1
1
TBST 1
1
1
1
1
1
ill3I
~ji"i';;!;s{l:
W,;
1",
If
}:;ll
Ii
',:!Yii'i;Vli,,;,/
iii:
AACK:
:
'-!-;
y
ARTRyl~~-~-~-~--+--+--+-~-~-~-~~
1
OBBI
1
0[0-63]
~---+---+--+---+--{
1
1
In
1
1
I
1
T A
iif'ii/;::!iir'ofi:;::Y
ORTRY:
\'---I--'/""";;~»o_,;'O_i'_O?'04"'-:"',o'''''';\-+...L~",,";J,,,,,;:=i,.i,;,,,--,
-+--_+-1
L::.Ai' = :' : ...
;;'"",Vj':"""
i, .... , , ' , , ' ' ' ' ' ' ' , i ' ....
,:~i""l:
~
2
I
3
4
5
6
7 I 8
9
10
11
12
13
14
Figure 8-17. Single-Beat Reads Showing Data-Delay Controls
8-30
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
