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Secondary Page
Table Search
Generate PA Using Primary Hash Function
PA
~
Base PA of PTEG
Otherwise
Otherwis~
PTE [VSID, API, H,
V]
=
Segment Descriptor [VSIDj, EA[APlj, 1, 1
Secondary Page Table
Search Hit
Last PTE in PTEG
~J:::~"
(See Figure 5-9)
Instruction Access
Data Access
IS I Exception
DSI Exception
Figure 5-10. Secondary Page Table Search Flow
The LSU initiates out-of-order accesses without knowledge of whether it is legal to do so.
Therefore, the MMU does not perform hardware table search due to TLB misses until the
request is required by the program flow. In these out-of-order cases, the MMU does detect
protection violations and whether a dcbz instruction specifies a page marked as
write-through or cache-inhibited. The MMU also detects alignment exceptions caused by
the dcbz instruction and prevents the changed bit in the PTE from being updated
erroneously in these cases.
If an MMU register is being accessed by an instruction in the instruction stream, the IMMU
stalls for one translation cycle to perform that operation. The sequencer serializes
instructions to ensure the data correctness. For updating the IBATs and SRs, the sequencer
classifies those operations as fetch serializing. After such an instruction is dispatched, the
instruction buffer is flushed and the fetch stalls until the instruction completes. However,
for reading from the IBATs, the operation is classified as execution serializing. As long as
the LSU ensures that all previous instructions can be executed, subsequent instructions can
be fetched and dispatched.
Chapter 5. Memory Management
5-33
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