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1.
In cycle 1, instructions 0 and 1 are dispatched to the IU2 and FPU, respectively.
Notice that for instructions to be dispatched they must be assigned positions in the
completion queue. In this case, since the completion queue was empty, instructions
o
and 1 take the two lowest entries in the completion queue. Instructions 2 and 3 drop
into the two dispatch positions in the instruction queue. Because there were two
positions available in the instruction queue in clock cycle 0, two instructions (4 and
5) are fetched into the instruction queue. Instruction 4 is a branch unconditional
instruction, which resolves immediately as taken. Because the branch is taken, it can
therefore be folded from the instruction queue.
2. In cycle 2, assume a BTIC hit occurs and target instructions 6 and 7 are fetched into
the instruction queue, replacing the folded b instruction (4) and instruction 5.
Instruction 0 completes, writes back its results and vacates the completion queue by
the end of the clock cycle. Instruction 1 enters the second FPU execute stage,
instruction 2 is dispatched to the IU2, and instruction 3 is dispatched into the first
FPU execute stage. Because the taken branch instruction (4) does not update either
CTR or LR, it does not require a position in the completion queue and can be folded.
3. In cycle 3, target instructions (6 and 7) are fetched, replacing instructions 4 and 5 in
IQO and IQ 1. This replacement on taken branches is called branch folding.
Instruction 1 proceeds through the last of the three FPU execute stages. Instruction
2 has executed but must remain in the completion queue until instruction 1
completes. Instruction 3 replaces instruction 1 in the second stage of the FPU, and
instruction 6 replaces instruction 3 in the first stage. Also, as will be shown in cycle
4, there is a single-cycle stall that occurs when the FPU pipeline is full.
Because there were three vacancies in the instruction queue in the previous clock
cycle, instructions 8-11 are fetched in this clock cycle.
4. Instruction 1 completes in cycle 4, allowing instruction 2 to complete. Instructions
3 and 6 continue through the FPU pipeline. Although instruction 7 is in IQ 1, it
cannot be dispatched because the FPU is busy, and because instruction 7 cannot be
dispatched neither can instruction 8. The additional cycle stall allows the instruction
queue to be completely filled. Because there was one opening in the instruction
queue in clock cycle 3, one instruction is fetched (12) and the instruction queue is
full.
5. In cycle 5, instruction 3 completes, allowing instruction 7 to be dispatched to the
FPU, which in turn allows instruction 8 to be dispatched to the IU2. Instructions 9
and 10 drop to the dispatch positions in the instruction queue. No instructions are
fetched in this clock cycle because there were no vacant IQ entries in clock cycle 4.
6. In cycle 6, instruction 6 completes, instruction 7 is in stage 2 of the FPU execute
stage, and although instruction 8 has executed, it must wait for instruction 7 to
complete. The two integer instructions, 9 and 10, are dispatched to the IU2 and lUI,
respectively. Fetching resumes with instructions 13 and 14.
Chapter 6. Instruction Timing
6-13
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