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The address transfer can be terminated with the requirement to retry if ARTRY is asserted
anytime during the address tenure and through the cycle following AACK. The assertion
causes the entire transaction (address and data tenure) to be rerun. As a snooping device,
the MPC750 asserts ARTRY for a snooped transaction that hits modified data in the data
cache that must be written back to memory, or if the snooped transaction could not be
serviced. As a bus master, the MPC750 responds to an assertion of ARTRY by aborting the
bus transaction and re-requesting the bus. Note that after recognizing an assertion of
ARTRY and aborting the transaction in progress, the MPC750 is not guaranteed to run the
same transaction the next time it is granted the bus due to internal reordering of load and
store operations.
If an address retry is required, the ARTRY response will be asserted by a bus snooping
device as early as the second cycle after the assertion of TS. Once asserted, ARTRY must
remain asserted through the cycle after the assertion of AACK. The assertion of ARTRY
during the cycle after the assertion of AACK is referred to as a qualified ARTRY. An earlier
assertion of ARTRY during the address tenure is referred to as an early ARTRY.
As a bus master, the MPC750 recognizes either an early or qualified ARTRY and prevents
the data tenure associated with the retried address tenure. If the data tenure has already
begun, the MPC750 aborts and terminates the data tenure immediately even if the burst data
has been received. If the assertion of ARTRY is received up to or on the bus cycle following
the first (or only) assertion of T A for the data tenure, the MPC750 ignores the first data beat,
and if it is a load operation, does not forward data internally to the cache and execution
units. If ARTRY is asserted after the first (or only) assertion of TA, improper operation of
the bus interface may result.
During the clock of a qualified ARTRY, the MPC750 also determines if it should negate BR
and ignore
EO
on the following cycle. On the following cycle, only the snooping master
that asserted ARTRY and needs to perform a snoop copy-back operation is allowed to assert
BR. This guarantees the snooping master an opportunity to request and be granted the bus
before the just-retried master can restart its transaction. Note that a nonclocked bus arbiter
may detect the assertion of address bus request by the bus master that asserted ARTRY, and
return a qualified bus grant one cycle earlier than shown in Figure 8-7.
Note that if the MPC750 asserts ARTRY due to a snoop operation, and asserts BR in the
bus cycle following ARTRY in order to perform a snoop push to memory it may be several
bus cycles later before the MPC750 will be able to accept a BG. (The delay in responding
to the assertion of BG only occurs during snoop pushes from the L2 cache.) The bus arbiter
should keep BG asserted until it detects BR negated or TS asserted from the MPC750
indicating that the snoop copy-back has begun. The system should ensure that no other
address tenures occur until the current snoop push from the MPC750 is completed. Snoop
push delays can also be avoided by operating the L2 cache in write-through mode so no
snoop pushes are required by the L2 cache.
8-18
MPC750 RISC Microprocessor User's Manual
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