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2.3.4.3 Load and Store Instructions
Load and store instructions are issued and translated in program order; however, the
accesses can occur out of order. Synchronizing instructions are provided to enforce strict
ordering. This section describes the load and store instructions, which consist of the
following:
•
Integer load instructions
•
Integer store instructions
•
Integer load and store with byte-reverse instructions
•
Integer load and store multiple instructions
•
Floating-point load instructions
•
Floating-point store instructions
•
Memory synchronization instructions
Implementation Notes-The following
describes
how
the
MPC750
handles
misalignment:
The MPC750 provides hardware support for misaligned memory accesses. It performs
those accesses within a single cycle if the operand lies within a double-word boundary.
Misaligned memory accesses that cross a double-word boundary degrade performance.
For string operations, the hardware makes no attempt to combine register values to reduce
the number of discrete accesses. Combining stores enhances performance if store gathering
is enabled and the accesses meet the criteria described in Section 6.4.7, "Integer Store
Gathering." Note that the PowerPC architecture requires load/store multiple instruction
accesses to be aligned. At a minimum, additional cache access cycles are required.
Although many unaligned memory accesses are supported in hardware, the frequent use of
them is discouraged since they can compromise the overall performance of the processor.
Accesses that cross a translation boundary may be restarted. That is, a misaligned access
that crosses a page boundary is completely restarted if the second portion of the access
causes a page fault. This may cause the first access to be repeated.
On some processors, such as the 603, a TLB reload would cause an instruction restart. On
the MPC750, TLB reloads are done transparently and only a page fault causes a restart.
2.3.4.3.1 Self-Modifying Code
When a processor modifies a memory location that may be contained in the instruction
cache, software must ensure that memory updates are visible to the instruction fetching
mechanism. This can be achieved by the following instruction sequence:
dcbst
lupdate memory
sync
Iwait for update
icbi
Iremove (invalidate) copy in instruction cache
isync
Iremove copy in own instruction buffer
Chapter 2. MPC750 Processor Programming Model
2-45
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