Address Pipelining And Split-Bus Transactions - Motorola MPC750 User Manual

8.2.2 Address Pipelining and Split-Bus Transactions
The MPC750 protocol provides independent address and data bus capability to support
pipelined and split-bus transaction system organizations. Address pipelining allows the
address tenure of a new bus transaction to begin before the data tenure of the current
transaction has finished. Split-bus transaction capability allows other bus activity to occur
(either from the same master or from different masters) between the address and data
tenures of a transaction.
While this capability does not inherently reduce memory latency, support for address
pipelining and split-bus transactions can greatly improve effective bus/memory throughput.
For this reason, these techniques are most effective in shared-memory multimaster
implementations where bus bandwidth is an important measurement of system
performance.
External arbitration is required in systems in which multiple devices must compete for the
system bus. The design of the external arbiter affects pipelining by regulating address bus
grant (BG), data bus grant (DBG), and address acknowledge (AACK) signals. For example,
a one-level pipeline is enabled by asserting AACK to the current address bus master and
granting mastership of the address bus to the next requesting master before the current data
bus tenure has completed. Two address tenures can occur before the current data bus tenure
completes.
The MPC750 can pipeline its own transactions to a depth of one level (intraprocessor
pipelining); however, the MPC750 bus protocol does not constrain the maximum number
of levels of pipelining that can occur on the bus between multiple masters (interprocessor
pipelining). The external arbiter must control the pipeline depth and synchronization
between masters and slaves.
In a pipe lined implementation, data bus tenures are kept in strict order with respect to
address tenures. However, external hardware can further decouple the address and data
buses, allowing the data tenures to occur out of order with respect to the address tenures.
This requires some form of system tag to associate the out-of-order data h·ansaction with
the proper originating address transaction (not defined for the MPC750 interface).
Individual bus requests and data bus grants from each processor can be used by the system
to implement tags to support interprocessor, out-of-order transactions.
The MPC750 supports a limited intraprocessor out-of-order, split-transaction capability via
the data bus write only (DBWO) signal. For more information about using DBWO, see
Section 8.10, "Using Data Bus Write Only."
Chapter 8. System Interface Operation
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