Reset Processing State; Table 7-1 Processing States - Motorola DSP56800 Manual

Chapter 7
Interrupts and the Processing States
The DSP56800 Family processors have six processing states and are always in one of these states (see
Table 7-1). Each processing state is described in detail in the following sections except the debug
processing state, which is discussed in Section 9.3, "OnCE Port," on page 9-4. In addition, special cases of
interrupt pipelines are discussed at the end of the section. Section 8.10, "Interrupts," on page 8-30
discusses software techniques for interrupt processing.
State
Reset The state where the DSP core is forced into a known reset state. Typically, the first
program instruction is fetched upon exiting this state.
Normal The state of the DSP core where instructions are normally executed.
Exception The state of interrupt processing, where the DSP core transfers program control from its
current location to an interrupt service routine using the interrupt vector table.
Wait A low-power state where the DSP core is shut down but the peripherals and interrupt
machine remain active.
Stop A low-power state where the DSP core, the interrupt machine, and most (if not all) of the
peripherals are shut down.
Debug The state where the DSP core is halted and all registers in the On-Chip Emulation
(OnCE) port of the processor are accessible for program debug.
7.1

Reset Processing State

The processor enters the reset processing state when the external RESET pin is asserted and a hardware
reset occurs. On devices with a computer operating properly (COP) timer, it is also possible to enter the
reset processing state when this timer reaches zero. The DSP is typically held in reset during the power-up
process through assertion of the RESET pin, making this the first processing state entered by the DSP. The
reset state performs the following:
1. Resets internal peripheral devices
2. Sets the M01 modifier register to $FFFF
3. Clears the interrupt priority register (IPR)
4. Sets the wait state fields in the bus control register (BCR) to their maximum value, thereby
inserting the maximum number of wait states for all external memory accesses
Table 7-1. Processing States
Description
Interrupts and the Processing States 7-1