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•
All other implementation-specific instructions
• Architecturally-allowed extended opcodes
2.3.2 Addressing Modes
This section provides an overview of conventions for addressing memory and for
calculating effective addresses as defined by the PowerPC architecture for 32-bit
implementations. For more detailed information, see "Conventions," in Chapter 4,
"Addressing Modes and Instruction Set Summary," of The Programming Environments
Manual.
2.3.2.1 Memory Addressing
A program references memory using the effective (logical) address computed by the
processor when it executes a memory access or branch instruction or when
it
fetches the
next sequential instruction.
Bytes in memory are numbered consecutively starting with zero. Each number is the
address of the corresponding byte.
2.3.2.2 Memory Operands
Memory operands may be bytes, half words, words, or double words, or, for the load/store
multiple and load/store string instructions, a sequence of bytes or words. The address of a
memory operand is the address of its first byte (that is, of its lowest-numbered byte).
Operand length is implicit for each instruction. The PowerPC architecture supports both
big-endian and little-endian byte ordering. The default byte and bit ordering is big-endian.
See "Byte Ordering," in Chapter 3, "Operand Conventions," of The Programming
Environments Manual for more information about big- and little-endian byte ordering.
The operand of a single-register memory access instruction has a natural alignment
boundary equal to the operand length. In other words, the "natural" address of an operand
is an integral multiple of the operand length. A memory operand is said to be aligned if it
is aligned at its natural boundary; otherwise it is misaligned. For a detailed discussion about
memory operands, see Chapter 3, "Operand Conventions," of The Programming
Environments Manual.
2.3.2.3 Effective Address Calculation
An effective address is the 32-bit sum computed by the processor when executing a
memory access or branch instruction or when fetching the next sequential instruction. For
a memory access instruction, if the sum of the effective address and the operand length
exceeds the maximum effective address, the memory operand is considered to wrap around
from the maximum effective address through effective address 0, as described in the
following paragraphs.
Effective address computations for both data and instruction accesses use 32-bit unsigned
binary arithmetic. A carry from bit 0 is ignored.
Chapter 2. MPC750 Processor Programming Model
2-35
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