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Table 7-1. Transfer Type Encodings for MPC750 Bus Master (Continued)
MPC750 Bus
Transaction
60x Bus
Master
Source
TTO
TTl
TT2
TT3
TT4
Specification
Transaction
Transaction
Command
N/A
N/A
0
0
1
1
1
Reserved
-
N/A
N/A
0
1
0
1
1
Read-with-no-
Single-beat
intent-to-cache
read or burst
N/A
N/A
0
1
1
1
1
Reserved
-
N/A
N/A
1
X
X
1
1
Reserved
-
Note:
1
Address-only transaction occurs if enabled by setting HIDO[ABE] bit to 1.
Table 7-2 describes the 60x bus specification transfer encodings and the MPC750 bus
snoop response on an address hit.
Table 7-2. MPC750 Snoop Hit Response
60x Bus Specification
MPC750 Bus
Transaction
TTO
TTl
TT2
TT3
TT4
Snooper;
Command
Action on Hit
Clean block
Address only
0
0
0
0
0
N/A
Flush block
Address only
0
0
1
0
0
N/A
sync
Address only
0
1
0
0
0
N/A
Kill block
Address only
0
1
1
0
0
Flush, cancel
reservation
eieio
Add ress on Iy
1
0
0
0
0
N/A
External control word write
Single-beat write
1
0
1
0
0
N/A
TLB Invalidate
Address only
1
1
0
0
0
N/A
External control word read
Single-beat read
1
1
1
0
0
N/A
Iwarx
Address only
0
0
0
0
1
N/A
reservation
set
Reserved
-
0
0
1
0
1
N/A
tlbsync
Address only
0
1
0
0
1
N/A
icbi
Address only
0
1
1
0
1
N/A
Reserved
-
1
X
X
0
1
N/A
Write-with-flush
Single-beat write or burst
0
0
0
1
0
Flush, cancel
reservation
Write-with-kill
Single-beat write or burst
0
0
1
1
0
Kill, cancel
reservation
Read
Single-beat read or burst
0
1
0
1
0
Clean or flush
Read-with-intent-to-modify
Burst
0
1
1
1
0
Flush
7-10
MPC750 RISC Microprocessor User's Manual
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