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by disabling the cache. This can potentially cause coherency errors. For example, a debf
instruction that hits a modified cache block in the disabled cache will cause a copyback to
memory of potentially stale data.
3.4.1.3 Data Cache Locking
The contents of the data cache can be locked by setting the data cache lock bit,
HIDO[DLOCK). A data access that hits in a locked data cache is serviced by the cache.
However, all accesses that miss in the locked cache are propagated to the L2 cache or 60x
bus as single-beat transactions. Note that the CI signal always reflects the state of the
caching-inhibited memory/cache access attribute (the I bit) independent of the state of
HIDO[DLOCK).
The MPC750 treats snoop hits to a locked data cache the same as snoop hits to an unlocked
data cache. However, any cache block invalidated by a snoop hit remains invalid until the
cache is unlocked.
The setting of the DLOCK bit must be preceded by a sync instruction to prevent the data
cache from being locked during a data access.
3.4.1.4 Instruction Cache Flash Invalidation
The instruction cache is automatically invalidated when the MPC750 is powered up and
during a hard reset. However, a soft reset does not automatically invalidate the instruction
cache. Software must use the HIDO instruction cache flash invalidate bit (HIDO[ICFI)) if
instruction cache invalidation is desired after a soft reset. Once HIDO[ICFI) is set through
an mtspr operation, the MPC750 automatically clears this bit in the next clock cycle
(provided that the instruction cache is enabled in the HIDO register).
Note that some PowerPC microprocessors accomplish instruction cache flash invalidation
by setting and clearing HIDO[ICFI) with two consecutive mtspr instructions (that is, the bit
is not automatically cleared by the microprocessor). Software that has this sequence of
operations does not need to be changed to run on the MPC750.
3.4.1.5 Instruction Cache Enabling/Disabling
The instruction cache may be enabled or disabled through the use of the instruction cache
enable bit, HIDO[ICE). HIDO[ICE) is cleared on power-up, disabling the instruction cache.
When the instruction cache is in the disabled state (HID [ICE)
=
0), the cache tag state bits
are ignored, and all instruction fetches are propagated to the L2 cache or 60x bus as
single-beat transactions. Note that the CI signal always reflects the state of the
caching-inhibited memory/cache access attribute (the I bit) independent of the state of
HIDO[ICE). Also note that disabling the instruction cache does not affect the translation
logic; translation for instruction accesses is controlled by MSR[IR).
3-14
MPC750 RISC Microprocessor
User's
Manual
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