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2.3.2.4.3
Instruction-Related Exceptions
There are two kinds of exceptions in the MPC750---those caused directly by the execution
of an instruction and those caused by an asynchronous event (or interrupts). Either may
cause components of the system software to be invoked.
Exceptions can be caused directly by the execution of an instruction as follows:
•
An attempt to execute an illegal instruction causes the illegal instruction (program
exception) handler to be invoked. An attempt by a user-level program to execute the
supervisor-level instructions listed below causes the privileged instruction (program
exception) handler to be invoked. The MPC750 provides the following
supervisor-level instructions:
dcbi, mfmsr, mfspr, mfsr, mfsrin, mtmsr, mtspr,
mtsr, mtsrin, rfi, tlbie,
and
tlbsync.
Note that the privilege level of the
mfspr
and
mtspr
instructions depends on the SPR encoding.
•
Any
mtspr, mfspr,
or
mftb
instruction with an invalid SPR (or TBR) field causes
an illegal type program exception. Likewise, a program exception is taken if
user-level software tries to access a supervisor-level SPR. An
mtspr
instruction
executing in supervisor mode (MSR[PR]
=
0) with the SPR field specifying HID!
or PVR (read-only registers) executes as a no-op.
•
An attempt to access memory that is not available (page fault) causes the lSI or DSI
exception handler to be invoked.
•
The execution of an
sc
instruction invokes the system call exception handler that
permits a program to request the system to perform a service.
• The execution of a trap instruction invokes the program exception trap handler.
• The execution of an instruction that causes a floating-point exception while
exceptions are enabled in the MSR invokes the program exception handler.
A detailed description of exception conditions is provided in Chapter 4, "Exceptions."
2.3.3
Instruction Set Overview
This section provides a brief overview of the PowerPC instructions implemented in the
MPC750 and highlights any special information with respect to how the MPC750
implements a particular instruction. Note that the categories used in this section correspond
to those used in Chapter 4, "Addressing Modes and Instruction Set Summary," in The
Programming Environments Manual. These categorizations are somewhat arbitrary and are
provided for the convenience of the programmer and do not necessarily reflect the PowerPC
architecture specification.
Note that some instructions have the following optional features:
•
CR Upd~te-The dot (.) suffix on the mnemonic enables the update of the CR.
•
Overflow option-The
0
suffix indicates that the overflow bit in the XER is enabled.
Chapter 2. MPC750 Processor Programming Model
2-37
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