Table of Contents
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Paragraph
Number
2.3.4.4
2.3.4.4.1
2.3.4.4.2
2.3.4.4.3
2.3.4.4.4
2.3.4.5
2.3.4.6
2.3.4.6.1
2.3.4.6.2
2.3.4.7
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.3.1
2.3.5.4
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.3.1
2.3.6.3.2
2.3.6.3.3
2.3.7
3.1
3.2
3.3
3.3.1
3.3.2
3.3.2.1
3.3.3
3.3.4
3.3.5
3.3.5.1
3.3.5.2
3.3.5.3
vi
CONTENTS
Title
Page
Number
Branch and Flow Control Instructions ....................................................... 2-53
Branch Instruction Address Calculation ................................................. 2-53
Branch Instructions ................................................................................ 2-54
Condition Register Logical Instructions ................................................ 2-54
Trap Instructions ................................................................................... .2-55
System Linkage Instruction-UISA .......................................................... 2-55
Processor Control Instructions-UISA ...................................................... 2-56
Move to/from Condition Register Instructions ...................................... 2-56
Move to/from Special-Purpose Register Instructions (UISA) ............... 2-56
Memory Synchronization Instructions-UISA .......................................... 2-59
PowerPC VEA Instructions ............................................................................ 2-60
Processor Control Instructions-VEA ....................................................... 2-60
Memory Synchronization Instructions-VEA .............. , ............................ 2-61
Memory Control Instructions-VEA ......................................................... 2-62
User-Level Cache Instructions-VEA ................................................... 2-62
Optional External Control Instructions ...................................................... 2-64
PowerPC OEA Instructions ............................................................................ 2-65
System Linkage Instructions-OEA .......................................................... 2-65
Processor Control Instructions-OEA ....................................................... 2-65
Memory Control Instructions-OEA ......................................................... 2-66
Supervisor-Level Cache Management Instruction-(OEA) .................. 2-66
Segment Register Manipulation Instructions (OEA) ............................. 2-67
Recommended Simplified Mnemonics .......................................................... 2-68
Chapter 3
Data Cache Organization ...................................................................................... 3-3
Instruction Cache Organization ............................................................................ 3-4
Memory and Cache Coherency ........................................................................... .3-5
Memory/Cache Access Attributes (WIMG Bits) ............................................. 3-6
MEl Protocol .................................................................................................... 3-7
MEl Hardware Considerations ..................................................................... 3-9
Coherency Precautions in Single Processor Systems ..................................... 3-10
Coherency Precautions in Multiprocessor Systems ....................................... 3-10
MPC750-lnitiated Load/Store Operations ...................................................... 3-10
Performed Loads and Stores ....................................................................... 3-11
Sequential Consistency of Memory Accesses ........................................... .3-11
Atomic Memory References ...................................................................... 3-11
MPC750 RISC Microprocessor User's Manual
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