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3.5.5 Data Cache-Block-Push Operation
When a cache block in the MPC750 is snooped and hit by another bus master and the data
is modified, the cache block must be written to memory and made available to the snooping
device. The cache block that is hit is said to be pushed out onto the 60x bus. The MPC750
supports two kinds of push operations-normal push operations and enveloped
high-priority push operations, which are described in Section 3.5.5.1, "Enveloped
High-Priority Cache-Block -Push Operation."
3.5.5.1 Enveloped High-Priority Cache-Block-Push Operation
In cases where the MPC750 has completed the address tenure of a read operation, and then
detects a snoop hit to a modified cache block by another bus master, the MPC750 provides
a high-priority push operation. If the address snooped is the same as the address of the data
to be returned by the read operation, ARTRY is asserted one or more times until the data
tenure of the read operation is completed. The cache-block-push transaction can be
enveloped within the address and data tenures of a read operation. This feature prevents
deadlocks in system organizations that support multiple memory-mapped buses.
More specifically, the MPC750 internally detects the scenario where a load request is
outstanding and the processor has pipelined a write operation on top of the load. Normally,
when the data bus is granted to the MPC750, the resulting data bus tenure is used for the
load operation. The enveloped high-priority cache block push feature defines a bus signal,
data bus write only (DBWO), which when asserted with a qualified data bus grant indicates
that the resulting data tenure should be used for the store operation instead. This signal is
described in Section 8.10, "Using Data Bus Write Only." Note that the enveloped
copy-back operation is an internally pipelined bus operation.
3.6 L 1 Caches and 60x Bus Transactions
The MPC750 transfers data to and from the cache in single-beat transactions of two words,
or in four-beat transactions of eight words which fill a cache block. Single-beat bus
transactions can transfer from one to eight bytes to or from the MPC750, and can be
misaligned. Single-beat transactions can be caused by cache write-through accesses,
caching-inhibited accesses (WIMG == x1xx), accesses when the cache is disabled
(HIDO[DCE] bit is cleared), or accesses when the cache is locked (HIDO[DLOCK] bit is
cleared).
Burst transactions on the MPC750 always transfer eight words of data at a time, and are
aligned to a double-word boundary. The MPC750 transfer burst (TBST) output signal
indicates to the system whether the current transaction is a single-beat transaction or
four-beat burst transfer. Burst transactions have an assumed address order. For cacheable
read operations, instruction fetches, or cacheable, non-write-through write operations that
miss the cache, the MPC750 presents the double-word-aligned address associated with the
load/store instruction or instruction fetch that initiated the transaction.
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MPC750 RISC Microprocessor User's Manual
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