Table of Contents
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Figure
Number
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1-2
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1-5
1-6
2-1
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2-3
2-4
2-5
2-6
2-7
2-8
2-9
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5-1
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Illustrations
ILLUSTRATIONS
Title
Page
Number
MPC750 Microprocessor Block Diagram ........................................................... 1-3
Cache Organization ............................................................................................ 1-13
System Interface ................................................................................................. 1-16
MPC750 Microprocessor Signal Groups ........................................................... 1-18
MPC750 Microprocessor Programming Model-Registers .............................. 1-23
Pipeline Diagram ............................................................................................... 1-34
Programming Model-MPC750 Microprocessor Registers ................................ 2-2
Instruction Address Breakpoint Register ............................................................. 2-9
Hardware Implementation-Dependent Register 0 (HIDO) ................................... 2-9
Hardware Implementation-Dependent Register 1 (HID 1) ................................. 2-13
Monitor Mode Control Register 0 (MMCRO) ................................................... 2-14
Monitor Mode Control Register 1 (MMCRl) ................................................... 2-16
Performance Monitor Counter Registers (PMCl-PMC4) ................................. 2-16
Sampled instruction Address Registers (SIA) ................................................... 2-20
Instruction Cache Throttling Control Register (ICTC) ...................................... 2-21
Thermal Management Registers 1-2 (THRMl-THRM2) ................................ 2-22
Thermal Management Register 3 (THRM3) ...................................................... 2-23
L2 Cache Control Register (L2CR) ................................................................... 2-24
Cache Integration ................................................................................................. 3-2
Data Cache Organization ..................................................................................... 3-4
Instruction Cache Organization ........................................................................... 3-5
MEl Cache Coherency Protocol-State Diagram (WIM == 00l) ......................... 3-8
PLRU Replacement Algorithm .......................................................................... 3-19
Double-Word Address Ordering-Critical Double Word First.. ....................... 3-23
Bus Interface Address Buffers ........................................................................... 3-31
Machine Status SaveIRestore Register 0 (SRRO) ................................................ 4-7
Machine Status SaveIRestore Register 1 (SRRl) ................................................ 4-7
Machine State Register (MSR) ............................................................................ 4-8
MMU Conceptual Block Diagram-32-Bit Implementations ............................. 5-6
MPC750 Microprocessor IMMU Block Diagram ............................................... 5-7
MPC750 Microprocessor DMMU Block Diagram .............................................. 5-8
Address Translation Types ................................................................................ 5-10
General Flow of Address Translation (Real Addressing Mode and Block) ...... 5-13
General Flow of Page and Direct-Store Interface Address Translation ............ 5-15
Segment Register and DTLB Organization ....................................................... 5-26
Page Address Translation Flow-TLB Hit.. ...................................................... 5-29
xvii
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