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source data to the execution unit. The register files and rename register have sufficient
bandwidth to allow dispatch of two instructions per clock under most conditions.
The MPC750's BPU decodes and executes branches immediately after they are fetched.
When a conditional branch cannot be resolved due to a CR data dependency, the branch
direction is predicted and execution continues from the predicted path. If the prediction is
incorrect, the following steps are taken:
1. The instruction queue is purged and fetching continues from the correct path.
2. Any instructions ahead of the predicted branch in the completion queue are allowed
to complete.
3. Instructions after the mispredicted branch are purged.
4. Dispatching resumes from the correct path.
After an execution unit finishes executing an instruction, it places resulting data into the
appropriate GPR or FPR rename register. The results are then stored into the correct GPR
or FPR during the write-back stage. If a subsequent instruction needs the result as a source
operand, it is made available simultaneously to the appropriate execution unit, which allows
a data-dependent instruction to be decoded and dispatched without waiting to read the data
from the register file. Branch instructions that update either the LR or CTR write back their
results in a similar fashion.
The following section describes this process in greater detail.
6.3.1 General Instruction Flow
As many as four instructions can be fetched into the instruction queue (IQ) in a single clock
cycle. Instructions enter the IQ and are issued to the various execution units from the
dispatch queue. The MPC750 tries to keep the IQ full at all times, unless instruction cache
throttling is operating.
The number of instructions requested in a clock cycle is determined by the number of
vacant spaces in the IQ during the previous clock cycle. This is shown in the examples in
this chapter. Although the instruction queue can accept as many as four new instructions in
a single clock cycle, if only one IQ entry is vacant, only one instruction is fetched. Typically
instructions are fetched from the on-chip instruction cache, but they may also be fetched
from the branch target instruction cache (BTIC). If the instruction request hits in the BTIC,
it can usually present the first two instructions of the new instruction stream in the next
clock cycle, giving enough time for the next pair of instructions to be fetched from the
instruction cache with no idle cycles. If instructions are not in the BTIC or the on-chip
instruction cache, they are fetched from the L2 cache or from system memory.
The MPC750's instruction cache throttling feature, managed through the instruction cache
throttling control (ICTC) register, can lower the processor's overall junction temperature by
slowing the instruction fetch rate. See Chapter 10, "Power and Thermal Management."
6-8
MPC750 RISC Microprocessor User's Manual
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