Instruction Dispatch And Completion Considerations - Motorola MPC750 User Manual

MPC750 in much the same way as shown in Figure 6-6. The formula for the L2 cache
latency for instruction accesses is as follows:
1 processor clock
+
3 L2 clocks
+
1 processor clock
Therefore, if the L2 is operating in 2: I mode, the instruction fetch takes 8 processor clock
cycles. Additional factors can also affect this latency, including the type of memory used to
implement the L2 and whether the processor clock and L2 clocks are aligned immediately.
For more information about the L2 cache implementation, see Chapter 9, "L2 Cache
Interface Operation."
6.3.3 Instruction Dispatch and Completion Considerations
Several factors affect the MPC7 50' s ability to dispatch instructions at a peak rate of two per
cycle-the availability of the execution unit, destination rename registers, and completion
queue, as well as the handling of completion-serialized instructions. Several of these
limiting factors are illustrated in the previous instruction timing examples.
To reduce dispatch unit stalls due to instruction data dependencies, the MPC750 provides
a single-entry reservation station for the FPU, SRU, and each IU, and a two-entry
reservation station for the LSU. If a data dependency keeps an instruction from starting
execution, that instruction is dispatched to the reservation station associated with its
execution unit (and the rename registers are assigned), thereby freeing the positions in the
instruction queue so instructions can be dispatched to other execution units. Execution
begins during the same clock cycle that the rename buffer is updated with the data the
instruction is dependent on.
If both instructions in IQO and IQl require the same execution unit, the instruction in IQl
cannot be dispatched until the first instruction proceeds through the pipeline and provides
the subsequent instruction with a vacancy in the requested execution unit.
The completion unit maintains program order after instructions are dispatched from the
instruction queue, guaranteeing in-order completion and a precise exception model.
Completing an instruction implies committing execution results to the architected
destination registers. In-order completion ensures the correct architectural state when the
MPC750 must recover from a mispredicted branch or an exception.
Instruction state and all information required for completion is kept in the six-entry, first-
in/first -out completion queue. An completion queue entry is allocated for each instruction
when it is dispatched to an execute unit; if no entry is available, the dispatch unit stalls. A
maximum of two instructions per cycle may be completed and retired from the completion
queue, and the flow of instructions can stall when a longer-latency instruction reaches the
last position in the completion queue. Subsequent instructions cannot be completed and
retired until that longer-latency instruction completes and retires. Examples of this are
shown in Section 6.3.2.2, "Cache Hit," and Section 6.3.2.3, "Cache Miss."
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MPC750 RISC Microprocessor User's Manual