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cache control instructions
bus operations, 3-24
cache control, 3-13
dcbi,2-66
dcbt, 2-63
cache hit, 6-11
cache integration, 3-2
cache management instructions, A-27
cache miss, 6-14
cache operations
cache block push operations, 9-4
data cache transactions, 3-22
instruction cache block fill, 3-21
load/store operations, processor initiated, 3-10
operations, 3-18
overview, 3-1, 8-2
snoop response to bus transactions, 3-26
cache unit overview, 3-3
cache-inhibited accesses (I bit), 3-6
data cache configuration, 3-3
dcbf/dcbst execution, 9-4
icbi,9-4
instruction cache configuration, 3-4
instruction cache throttling, 10-10
LI cache and bus transactions, 3-22
L2 interface
cache configuration, 9-2
cache global invalidation, 9-7
cache initialization, 9-6
cache testing, 9-8
clock configuration, 9-9
dcbi,9-4
eieio, 9-4
L2 cache considerations, 6-15
L2 cache interface signals, 7-25
operation, 9-2
overview, 9-1
SRAM timing examples, 9-9
stwcx. execution, 9-4
sync, 9-4
load/store operations, processor initiated, 3-10
PLRU replacement, 3-19
stwcx. execution, 9-4
Changed (C) bit maintenance recording, 5-12, 5-23
Checkstop
signal, 7-22, 8-35
state, 4-16
CI
(cache inhibit) signal, 7-12
INDEX
Clock signals
PLL_CFGn, 7-30
SYSCLK,7-29
Compare instructions
floating-point, A-21
integer, A-18
Completion
completion unit resource requirements, 6-30
considerations, 6-16
definition, 6-1
Context synchronization, 2-36
Conventions, xxxiii, xxxvii, 6-1
COP/scan interface, 8-37
Copy-back mode, 6-27
CR (condition register)
CR logical instructions, 2-54, A-26
CR, description, 2-3
CTR register, 2-4
o
DABR (data address breakpoint register), 2-7
DAR (data address register), 2-6
Data bus
arbitration signals, 7-15, 8-8
bus arbitration, 8-19
data tenure, 8-7
data transfer, 7-17, 8-21
data transfer termination, 7-19, 8-22
Data cache
block push operation, 3-22
configuration, 3-3
DCFI, DCE, DLOCK bits, 3-13
organization, 3-4
Data organization in memory, 2-28
Data transfers
alignment, 8-15
burst ordering, 8-15
eciwx and ecowx instructions, alignment, 8-17
operand conventions, 2-28
signals, 8-21
DBB (data bus busy) signal, 7-16, 8-8, 8-20
DBDIS (data bus disable) signal, 7-19
DBG (data bus grant) signal, 7-15, 8-8
DBWO (data bus write only) signal, 7-16, 8-8,
8-21,8-37
dcbi,2-66
dcbt, 2-63
CKSTP _IN/CKSTP _OUT (checkstop input/output)
DEC (decrementer register), 2-7
Decrementer exception, 4-19
Defined instruction class, 2-33
DHnlDLn (data bus) signals, 7-17
Dispatch
signals, 7-22
Classes of instructions, 2-32
Clean block operation, 3-26
CLK_OUT signal, 7-29
Index-2
consideration" 6-16
dispatch unit resource requirements, 6-30
MPC750 RISC Microprocessor User's Manual
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