Table of Contents
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Table
Number
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
7-1
7-2
7-3
7-4
7-5
7-6
8-1
8-2
8-3
8-4
9-1
10-1
10-2
10-3
10-4
10-5
11-1
Tables
TABLES
Page
Number
Title
IEEE Floating-Point Exception Mode Bits ....................................................... 4-10
MSR Setting Due to Exception ......................................................................... 4-12
System Reset Exception-Register Settings .................................................... 4-13
HIDO Machine Check Enable Bits .................................................................... 4-15
Machine Check Exception-Register Settings ................................................. 4-16
Trace Exception-SRR1 Settings ..................................................................... 4-20
Performance Monitor Interrupt Exception-Register Settings ......................... 4-21
Instruction Address Breakpoint Exception-Register Settings ........................ 4-22
System Management Interrupt Exception-Register Settings ......................... 4-23
Thermal Management Interrupt Exception-Register Settings ........................ 4-24
MMU Feature Summary ..................................................................................... 5-3
Access Protection Options for Pages ................................................................ 5-11
Translation Exception Conditions ..................................................................... 5-17
Other MMU Exception Conditions for the MPC750 Processor ....................... 5-18
MPC750 Microprocessor Instruction Summary-Control MMUs .................. 5-19
MPC750 Microprocessor MMU Registers ....................................................... 5-20
Table Search Operations to Update History Bits-TLB Hit Case ................... 5-22
Model for Guaranteed Rand C Bit Settings ..................................................... 5-24
Performance Effects of Memory Operand Placement ...................................... 6-26
TLB Miss Latencies .......................................................................................... 6-28
Branch Instructions ........................................................................................... 6-31
System Register Instructions ............................................................................. 6-31
Condition Register Logical Instructions ........................................................... 6-32
Integer Instructions ........................................................................................... 6-33
Floating-Point Instructions ................................................................................ 6-34
Load and Store Instructions .............................................................................. 6-36
Transfer Type Encodings for MPC750 Bus Master ........................................... 7-9
MPC750 Snoop Hit Response .......................................................................... 7-10
Data Transfer Size ............................................................................................. 7-11
Data Bus Lane Assignments ............................................................................. 7-17
DP[0-7] Signal Assignments ............................................................................ 7-18
IEEE Interface Pin Descriptions ....................................................................... 7-28
Transfer Size Signal Encodings ........................................................................ 8-14
Burst Ordering .................................................................................................. 8-15
Aligned Data Transfers ..................................................................................... 8-15
Misaligned Data Transfers (Four-Byte Examples) ........................................... 8-17
L2 Cache Control Register .................................................................................. 9-5
MPC750 Microprocessor Programmable Power Modes .................................. 10-2
THRMI and THRM2 Bit Field Settings ........................................................... 10-7
THRM3 Bit Field Settings ................................................................................ 10-7
Valid THRMI and THRM2 Bit Settings .......................................................... 10-9
ICTC Bit Field Settings .................................................................................. 10-11
Performance Monitor SPRs .............................................................................. 11-3
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