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In many cases, after the exception handler handles an exception, there is an attempt to
execute the instruction that caused the exception. Instruction execution continues until the
next exception condition is encountered. Recognizing and handling exception conditions
sequentially guarantees that the machine state is recoverable and processing can resume
without losing instruction results.
In this book, the following terms are used to describe the stages of exception processing:
Recognition
Taken
Handling
Exception recognition occurs when the condition that can cause an
exception is identified by the processor.
An exception is said to be taken when control of instruction
execution is passed to the exception handler; that is, the context is
saved and the instruction at the appropriate vector offset is fetched
and the exception handler routine is begun in supervisor mode.
Exception handling is performed by the software linked to the
appropriate vector offset. Exception handling is begun in supervisor
mode (referred to as privileged state in the architecture
specification).
Note that the PowerPC architecture documentation refers to exceptions as interrupts. In this
book, the term 'interrupt' is reserved to refer to asynchronous exceptions and sometimes to
the event that causes the exception. Also, the PowerPC architecture uses the word
'exception' to refer to IEEE-defined floating-point exception conditions that may cause a
program exception to be taken; see Section 4.5.7, "Program Exception (Ox00700)." The
occurrence of these IEEE exceptions may not cause an exception to be taken. IEEE-defined
exceptions are referred to as IEEE floating-point exceptions or floating-point exceptions.
4.1 MPC750 Microprocessor Exceptions
As specified by the PowerPC architecture, exceptions can be either precise or imprecise and
either synchronous or asynchronous. Asynchronous exceptions are caused by events
external to the processor's execution; synchronous exceptions are caused by instructions.
The types of exceptions are shown in Table 4-1. Note that all exceptions except for the
system management interrupt, thermal management, and performance monitor exception
are defined, at least to some extent, by the PowerPC architecture.
Table 4-1. MPC750 Microprocessor Exception Classifications
Synchronous/Asynchronous Precise/Imprecise
Exception Types
Asynchronous, nonmaskable
Imprecise
Machine check, system reset
Asynchronous, maskable
Precise
External interrupt, decrementer, system management interrupt,
performance monitor interrupt, thermal management interrupt
Synchronous
Precise
Instruction-caused exceptions
4-2
MPC750 RISC Microprocessor User's Manual
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