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Fetch
I
Maximum four-
I
per clock cycle
instruction fetch
I
BPU
I
J
Decode/Dispatch
I
I
Maximum thre e-instruction dispatch
(includes one branch
per clock cycle
instruction)
~----------------------
I
----------------EXec
lJie
Stage-'
I
I
I
I
I
I
I
,
I
!
I
I
I
FPU1
I
I
FPU2
LSU1
I
I
I
I
I
I I
I
I
SRU
FPU3
IU1
IU2
LSU2
I
I
+
I
I
I
-----------------------
-------------------
I
Complete (Write-back)
I
Maximum two -
completion per
Figure 6-2. Superscalar/Pipeline Diagram
The instruction pipeline stages are described as follows:
I
,
,
I
,
I
instruction
clock cycle
•
The instruction fetch stage includes the clock cycles necessary to request
instructions from the memory system and the time the memory system takes to
respond to the request. Instruction fetch timing depends on many variables, such as
whether the instruction is in the branch target instruction cache, the on-chip
instruction cache, or the L2 cache. Those factors increase when it is necessary to
fetch instructions from system memory, and include the processor-to-bus clock
ratio, the amount of bus traffic, and whether any cache coherency operations are
required.
Because there are so many variables, unless otherwise specified, the instruction
timing examples below assume optimal performance, that the instructions are
available in the instruction queue in the same clock cycle that they are requested. The
fetch stage ends when the instruction is dispatched.
•
The decode/dispatch stage consists of the time it takes to fully decode the instruction
and dispatch it from the instruction queue to the appropriate execution unit.
Instruction dispatch requires the following:
-
Instructions can be dispatched only from the two lowest instruction queue
entries, IQO and IQl.
-
A maximum of two instructions can be dispatched per clock cycle (although an
additional branch instruction can be handled by the BPU).
-
Only one instruction can be dispatched to each execution unit per clock cycle.
-
There must be a vacancy in the specified execution unit.
Chapter 6. Instruction Timing
6-5
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