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The PowerPC UISA registers are user-level. General-purpose registers (GPRs) and
floating-point registers (FPRs) are accessed through instruction operands. Access to
registers can be explicit (by using instructions for that purpose such as Move to
Special-Purpose Register (mtspr) and Move from Special-Purpose Register (mfspr)
instructions) or implicit as part of the execution of an instruction. Some registers are
accessed both explicitly and implicitly.
Implementation Note-The MPC750 fully decodes the SPR field of the instruction. If the
SPR specified is undefined, the illegal instruction program exception occurs. The
PowerPC's user-level registers are described as follows:
• User-level registers (UISA)-The user-level registers can be accessed by all
software with either user or supervisor privileges. They include the following:
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General-purpose registers (GPRs). The thirty-two GPRs (GPRO-GPR31) serve
as data source or destination registers for integer instructions and provide data
for generating addresses. See "General Purpose Registers (GPRs)," in Chapter 2,
"PowerPC Register Set," of The Programming Environments Manual for more
information.
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Floating-point registers (FPRs). The thirty-two FPRs (FPRO-FPR31) serve as
the data source or destination for all floating-point instructions. See
"Floating -Point Registers (FPRs )," in Chapter 2, "PowerPC Register Set," of The
Programming Environments Manual.
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Condition register (CR). The 32-bit CR consists of eight 4-bit fields, CRO-CR7,
that reflect results of certain arithmetic operations and provide a mechanism for
testing and branching. See "Condition Register (CR)," in Chapter 2, "PowerPC
Register Set," of The Programming Environments Manual.
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Floating-point status and control register (FPSCR). The FPSCR contains all
floating-point exception signal bits, exception summary bits, exception enable
bits, and rounding control bits needed for compliance with the IEEE 754
standard. See "Floating-Point Status and Control Register (FPSCR)," in
Chapter 2, "PowerPC Register Set," of The Programming Environments
Manual.
The remaining user-level registers are SPRs. Note that the PowerPC architecture
provides a separate mechanism for accessing SPRs (the mtspr and mfspr
instructions). These instructions are commonly used to explicitly access certain
registers, while other SPRs may be more typically accessed as the side effect of
executing other instructions.
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Integer exception register (XER). The XER indicates overflow and carries for
integer operations. See "XER Register (XER)," in Chapter 2, "PowerPC Register
Set," of The Programming Environments Manual for more information.
Implementation Note-To allow emulation of the lscbx instruction defined by
the POWER architecture, XER[16-23] is implemented so that they can be read
with mfspr[XER] and written with mtxer[XER] instructions.
Chapter 2. MPC750 Processor Programming Model
2-3
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