Mcbsp_Xccr_Reg - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
11.3.40 McBSP Transmit Configuration Control Register (XCCR_REG)
The McBSP_XCCR_REG register is shown in
31
15 14
EXTCLKGATE PPCONNECT
R/W-0 R/W-0
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-16 Reserved
15 EXTCLKGATE
14 PPCONNECT
13-12 DXENDLY
11 XFULL_CYCLE
10-6 Reserved
5 DLB
4 Reserved
1208
Multichannel Buffered Serial Port (McBSP)
Preliminary
Figure 11-72. McBSP_XCCR_REG
13 12
DXENDLY
R/W-1
5 4
DLB Reserved
R/W-0 R-0
Table 11-59. McBSP_XCCR_REG Field Descriptions
Value Description
0 Reserved.
External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit
clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after
(clock is provided for FWID + 4 clock cycles, assuming that the FSX width, active, is FWID + 1
clock cycles); outside this window the external transmit clock is gated. The receive uses the same
gated transmit clock and transmit frame synchronization signals regardless of the CLKRM/FSRM
settings. When using this mode the frame synchronization signal must be active during reception of
the entire frame (FWID must be programmed accordingly) to ensure the proper receive process,
which requires at least 3 cycles after the frame complete to transfer the data into the receive buffer.
0 External clock gating disabled.
1 External clock gating enable.
Pair to pair connection. When set the DXENO pin is always set to 0, regardless of the frame
boundary, setting the tree state buffer as output.
0 non Pair-to-pair connection. The DX pin will go to high-impedance state when there is no frame to
transmit.
1 Pair-to-pair connection. When set, the DXENO pin is always set to 0, regardless of the frame
boundary, setting the tree state buffer as output. This means the DX pin will be driven outside valid
frame window. In that case, data sent by McBSP module during inactive channel are not
guaranteed.
When McBSPi.McBSP_SPCR1_REG[7] DXENA bit is set to one, this field selects the added delay
as follow:
0 8 ns
1h 14 ns (default)
2h 20 ns
3h 28 ns
Transmit full cycle mode select:
0 McBSP module operates in transmit half-cycle mode (transmit frame synchronization is sampled by
the opposite edge of the clock used to drive transmit data).
1 McBSP module operates in transmit full-cycle mode (transmit frame synchronization is sampled by
the same edge of the clock used to drive transmit data).
0 Reserved.
Digital Loopback. When this bit is set the transmit FSX, CLKX and DX are connected to FSR,
CLKR, DR. The outputs of the McBSP (CLKR/CLKX, FSR/FSX, DX are not enabled)
0 No DLB.
1 DLB.
0 Reserved.
© 2011, Texas Instruments Incorporated
Figure 11-72 and described in
Reserved
R-0
11 10
XFULL_CYCLE
R/W-0
3 2
XDMAEN
R/W-1
www.ti.com
Table 11-59.
8
Reserved
R-0
1 0
Reserved XDISABLE
R-0 R/W-0
SPRUGX9 – 15 April 2011
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