Mcbsp_Rcr1_Reg; Mcbsp_Rcr1_Reg Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
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Registers
11.3.6 McBSP Receive Control Register 1 (RCR1_REG
The McBSP_RCR1_REG register is shown in
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-15
Reserved
14-8
RFRLEN1
7-5
RWDLEN1
4-0
Reserved
1182
Multichannel Buffered Serial Port (McBSP)
Preliminary
Figure 11-38. McBSP_RCR1_REG
Reserved
R-0
Table 11-25. McBSP_RCR1_REG Field Descriptions
Value
Description
0
Reserved
Receive Frame Length 1.
Single-phase frame selected:
RFRLEN1=000 0000 - 1 word per frame
RFRLEN1=000 0001 - 2 words per frame.
RFRLEN1=111 1111 - 128 words per frame.
Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase.
(other values are reserved).
Receive Word Length 1
0
8 bits
1h
12 bits
2h
16 bits
3h
20 bits
4h
24 bits
5h
32 bits
6h
Reserved (do not use).
7h
Reserved (do not use).
0
Reserved
© 2011, Texas Instruments Incorporated
Figure 11-38
and described in
15 14
RFRLEN1
R/W-0
www.ti.com
Table
11-25.
8
7
5
4
RWDLEN1
Reserved
R/W-0
R-0
SPRUGX9 – 15 April 2011
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