Adma System Address Low Bits (Sd_Admasal); Adma System Address High Bits Register (Sd_Admasah); Adma System Address Low Bits (Sd_Admasal) Field Descriptions; Adma System Address High Bits Register (Sd_Admasah) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
9.4.30 ADMA System Address Low Bits Register (SD_ADMASAL)
This register holds the byte address of the executing command of the Descriptor table. The 32-bit
Address Descriptor uses the lower 32 bits of this register. At the start of ADMA, the Host Driver shall
set the start address of the Descriptor table.
The ADMA System address low bits register (SD_ADMASAL) is shown in
Table 9-40.
31
LEGENDR/W = Read/Write; R = Read only; -n = value after reset
Table 9-40. ADMA System Address Low Bits (SD_ADMASAL) Field Descriptions
Bit Field
31-0 ADMA_A32B

9.4.31 ADMA System Address High Bits Register (SD_ADMASAH)

The ADMA System address high bits register (SD_ADMASAH) is shown in
in Table 9-40.
Figure 9-59. ADMA System Address High Bits Register (SD_ADMASAH)
31
LEGENDR/W = Read/Write; R = Read only; -n = value after reset
Table 9-41. ADMA System Address High Bits Register (SD_ADMASAH) Field Descriptions
Bit Field
31-0 ADMA_A32B
1008
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Figure 9-58. ADMA System Address Low Bits (SD_ADMASAL)
Value Description
The ADMA increments this register address, which points to the next line, whenever fetching a
Descriptor line. When the ADMA Error Interrupt is generated, this register holds the valid Descriptor
address depending on the ADMA state. The Host Driver shall program the Descriptor Table on a
32-bit boundary and set the 32-bit boundary address to this register. ADMA2 ignores the lower 2
bits of this register and assumes it to be 00b.
Value Description
© 2011, Texas Instruments Incorporated
ADMA_A32B
R/W-0
ADMA_A32B
R/W-0
www.ti.com
Figure 9-58 and described in
0
Figure 9-58 and described
0
SPRUGX9 – 15 April 2011
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