Diag_Ctrl Register; Endian Register; Diag_Ctrl Register Field Descriptions; Endian Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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13.4.4.11 DIAG_CTRL Register

The diagnostic control register (DIAG_CTRL) is described in the figure and table below.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-2 Reserved
1 INV_ECRC
0 INV_LCRC

13.4.4.12 ENDIAN Register

The endian mode register (ENDIAN) is described in the figure and table below.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-2 Reserved
1-0 ENDIAN
SPRUGX9 – 15 April 2011
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Preliminary
Figure 13-23. DIAG_CTRL Register
Reserved
R-0
Table 13-26. DIAG_CTRL Register Field Descriptions
Value Description
0 Reserved
0 Write 1 to force inversion of LSB of ECRC for next one packet. It is self-cleared when the ECRC
error has been injected on one TLP.
0 Write 1 to force inversion of LSB of LCRC for next one packet. It is self-cleared when the ECRC
error has been injected on one TLP.
Figure 13-24. ENDIAN Register
Reserved
R-0
Table 13-27. ENDIAN Register Field Descriptions
Value Description
0 Reserved
0-3h Applicable in CBA version of PCIESS only. Not applicable to OCP bus.
© 2011, Texas Instruments Incorporated
Reserved
R-0
2
INV_ECRC
Reserved
R-0
Peripheral Component Interconnect Express (PCIe)
1 0
INV_LCRC
R/W-0 R/W-0
2 1
ENDIAN_MODE
R/W-0
Registers
16
16
0
1315