I2C Own Address Register (I2C_Psc); Clock Divider; I2C Clock Prescaler Register (I2C_Psc) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
7.3.23 I2C Clock Prescaler Register (I2C_PSC)
During an active mode (I2C_EN bit in I2C_CON register is set to 1), no
modification must be done in this register. Changing it may result in an
unpredictable behavior.
This register is used to specify the internal clocking of the I2C peripheral core.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-26. I2C Clock Prescaler Register (I2C_PSC) Field Descriptions
Bit Field
31-8 Reserved
7-0 PSC
890
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Figure 7-36. I2C Own Address Register (I2C_PSC)
Reserved
R-0
Value Description
0 Reserved
0-FFh Fast/Standard mode prescale sampling clock divider value.
The core uses this 8-bit value to divide the system clock (SCLK) and generates its own internal
sampling clock (ICLK) for Fast and Standard operation modes. The core logic is sampled at the
clock rate of the system clock for the module divided by (PSC + 1).
0h Divide by 1
1h Divide by 2
-
-
FFh Divide by 256
Value after reset is low (all 8 bits).
Figure 7-37. Clock Divider
SCLK
1/(PSC+1)
© 2011, Texas Instruments Incorporated
CAUTION
8 7
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0
PSC
R/W-0
ICLK
SPRUGX9 – 15 April 2011
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