Pcie_Cerr_Mask Register; Pcie_Cerr_Mask Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

13.4.9.6 PCIE_CERR_MASK Register

31
15 14
Reserved
R-0
7 6
BAD_DLLP_MSK BAD_TLP_MSK
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-14 Reserved
13 ADV_NFERR_MSK
12 RPLY_TMR_MSK
11-9 Reserved
8 RPLT_RO_MSK
7 BAD_DLLP_MSK
6 BAD_TLP_MSK
5-1 Reserved
0 RCVR_ERR_MSK
1378
Peripheral Component Interconnect Express (PCIe)
Preliminary
Figure 13-122. PCIE_CERR_MASK Register
13 12
ADV_NFERR_MSK RPLY_TMR_MSK
R/W-1 R/W-0
5
Table 13-130. PCIE_CERR_MASK Register Field Descriptions
Value Description
0 Reserved
1 Advisory Non-fatal Error Mask
0 Reply Timer Timeout Mask
0 Reserved
0 REPLAY_NUM Rollover Mask
0 Bad DLLP Mask
0 Bad TLP Mask
0 Reserved
0 Receiver Error Mask
© 2011, Texas Instruments Incorporated
Reserved
R-0
11
Reserved
R-0
Reserved
R-0
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16
9 8
RPLT_RO_MSK
R/W-0
1 0
RCVR_ERR_MSK
R/W-0
SPRUGX9 – 15 April 2011
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