Cm_Alwon_L3_Fast_Clkstctrl Register; Cm_Alwon_L3_Fast_Clkstctrl Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

14.7.11.13 CM_ALWON_L3_FAST_CLKSTCTRL Register

The CM_ALWON_L3_FAST_CLKSTCTRL register enables the domain power state transition. It
controls the software supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE
states. It also hold one status bit per clock input of the domain.
31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-108. CM_ALWON_L3_FAST_CLKSTCTRL Register Field Descriptions
Bit Field
31-10 Reserved
9 CLKACTIVITY_FAST_GCLK
8-2 Reserved
1-0 CLKTRCTRL
1490
Power, Reset, and Clock Management (PRCM) Module
Preliminary
Figure 14-93. CM_ALWON_L3_FAST_CLKSTCTRL Register
R-0
Value Description
0 Reserved
This field indicates the state of the L3 Fast clock for TPTC and TPCC in the
domain.
0 Corresponding clock is gated
1 Corresponding clock is active
0 Reserved
Controls the clock state transition of the RTC clock domain in Always ON
power domain.
0 NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may
however occur.
1h SW_SLEEP: Start a software forced sleep transition on the domain.
2h SW_WKUP: Start a software forced wake-up transition on the domain.
3h HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are
based upon hardware conditions.
© 2011, Texas Instruments Incorporated
10 9
CLKACTIVITY_FAST_GCLK
R-0
www.ti.com
8 2 1 0
Reserved CLKTRCTRL
R-0 R/W-1
SPRUGX9 – 15 April 2011
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