Mcbsp_Pcr_Reg - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
11.3.17 McBSP Pin Control Register (PCR_REG)
The McBSP_PCR_REG register is shown in
31
15 14
Reserved IDLE_EN
R-0 R/W-0
7 6
SCLKME CLKS_STAT
R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-15 Reserved
14 IDLE_EN
13 XIOEN
12 RIOEN
11 FSXM
10 FSRM
9 CLKXM
1192
Multichannel Buffered Serial Port (McBSP)
Preliminary
Figure 11-49. McBSP_PCR_REG
13 12
XIOEN RIOEN
R/W-0 R/W-0
5 4
DX_STAT DR_STAT
R/W-0 R-0
Table 11-36. McBSP_PCR_REG Field Descriptions
Value Description
0 Reserved.
Idle enable (legacy only).
This bit allows stopping all the clocks in the McBSP module. (legacy)
0 The McBSP is running
1 The clocks in the McBSP are shut off when both IDLE_EN=1 and his power domain is in idle mode
(Force idle or Smart idle)
Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2]. (legacy only)
0 DX, FSX and CLKX are configured as serial port pins and do not function as general-purpose I/Os.
1 DX pin is a general purpose output. FSX and CLKX are general purpose I/Os. These serial port
pins do not perform serial port operation.
Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2]. (legacy)
0 DR, FSR, CLKR and CLKS are configured as serial port pins and do not function as
general-purpose I/Os.
1 DR and CLKS pins are general purpose inputs; FSR and CLKR are general purpose I/Os. These
serial port pins do not perform serial port operation. The CLKS pin is affected by a combination of
RRST and RIOEN signals of the receiver.
Transmit Frame-Synchronization Mode.
0 Frame-synchronization signal derived from an external source.
1 Frame synchronization is determined by the SRG frame-synchronization mode bit FSGM in
SRGR2.
Receive Frame-Synchronization Mode.
0 Frame-Synchronization pulses generated by an external device. FSR is an input pin.
1 Frame synchronization generated internally by SRG. FSR is an output pin except when GSYNC=1
in SRGR.
Transmitter Clock Mode.
When digital loop-back mode set (McBSPi.McBSP_XCCR_REG[5] DLB=1), CLKXM bit is ignored.
The internal transmit clock (not the mcbspi_clkx pin) is driven by the internal SRG and mcbspi_clkx
pin is in high-impedance.
0 Transmitter clock is driven by an external clock with CLKX as an input pin.
1 CLKX is an output pin and is driven by the internal SRG.
© 2011, Texas Instruments Incorporated
Figure 11-49 and described in
Reserved
R-0
11 10
FSXM FSRM
R/W-0 R/W-0
3 2
FSXP FSRP
R/W-0 R/W-0
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Table 11-36.
16
9 8
CLKXM CLKRM
R/W-0 R/W-0
1 0
CLKXP CLKRP
R/W-0 R/W-0
SPRUGX9 – 15 April 2011
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