Boot Acknowledge Timeout When Using Cmd0; Boot Acknowledge Timeout When Cmd Held Low - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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9.2.8.5 Boot Acknowledge Timeout
Figure 9-17 shows DCRC event condition asserted when there is boot acknowledge timeout and CMD0
is used.
Figure 9-17. Boot Acknowledge Timeout When Using CMD0
clk
cmd
CMD0
dat0
Min. 74 clocks
required after
power is stable
to start boot
command.
t1
t1 - Data timeout counter is loaded and starts after CMD0.
t2 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.
t3 - Data timeout counter is loaded and starts.
t4 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.
t5 - Data timeout counter is loaded and starts after Data + CRC transmission.
t6 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.
Figure 9-18 shows DCRC event condition asserted when there is boot acknolwedge timeout and CMD
line is held low.
Figure 9-18. Boot Acknowledge Timeout When CMD Held Low
clk
cmd
dat0
S
50ms max
1 sec. max
t1 t2
t1 - Data timeout counter is loaded and starts after cmd line is tied to 0.
t2 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.
t3 - Data timeout counter is loaded and starts.
t4 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.
t5 - Data timeout counter is loaded and starts after Data + CRC transmission.
t6 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.
SPRUGX9 – 15 April 2011
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Preliminary
512 Bytes
S 010 E S E
+ CRC
50ms max
1 sec. max
t2 t3 t4
512 Bytes
010 E S E S
+ CRC
t5 t6
t3 t4
© 2011, Texas Instruments Incorporated
CMD0/reset
512 Bytes
S E
+ CRC
t5 t6
CMD1
512 Bytes
E
+ CRC
Boot Terminated
Min. 8 clocks + 48 clocks = 56 clocks required
from CMD signal high to next command.
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Architecture
CMD1 RESP CMD2 RESP CMD3
RESP CMD2 RESP CMD3 RESP
RESP
949