Read Fifo Control Register (Rfifoctl); Read Fifo Control Register (Rfifoctl) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers

10.3.45 Read FIFO Control Register (RFIFOCTL)

The Read FIFO control register (RFIFOCTL) is shown in
NOTE: The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO.
If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of
reset.
31
15
RNUMEVT
R/W-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-48. Read FIFO Control Register (RFIFOCTL) Field Descriptions
Bit Field Value
31-17 Reserved
16 RENA
15-8 RNUMEVT 0-FFh
3h-40h
41h-FFh
7-0 RNUMDMA 0-FFh
3h-10h
11h-FFh
1120
Multichannel Audio Serial Port (McASP)
Figure 10-82. Read FIFO Control Register (RFIFOCTL)
Reserved
Description
0 Reserved
Read FIFO enable bit.
0 Read FIFO is disabled. The RLVL bit in the Read FIFO status register (RFIFOSTS) is reset to 0
and pointers are initialized, that is, the Read FIFO is "flushed."
1 Read FIFO is enabled. If Read FIFO is to be enabled, it must be enabled prior to taking McASP
out of reset.
Read word count per DMA event (32-bit). When the Read FIFO contains at least RNUMEVT
words of data, then an AREVT (receive DMA event) is generated to the host/DMA controller. This
value should be set to a non-zero integer multiple of the number of serializers enabled as
receivers. This value must be set prior to enabling the Read FIFO.
0 0 words
1h 1 word
2h 2 words
3 to 64 words
Reserved
Read word count per transfer (32-bit words). Upon a receive DMA event from the McASP, the
Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of
McASP serializers used as receivers. This value must be set prior to enabling the Read FIFO.
0 0 words
1 1 word
2 2 words
3-16 words
Reserved
© 2011, Texas Instruments Incorporated
Preliminary
Figure 10-82
R-0
8 7
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and described in Table 10-48.
17
RNUMDMA
R/W-4h
SPRUGX9 – 15 April 2011
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16
RENA
R/W-0
0