Prescaler Clock Ratios Value; Value And Corresponding Interrupt Period - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Architecture
17.2.1.6 Timer Counting Rate
The timer counter is composed of a prescaler stage and a timer counter. Prescaler stage is clocked
with the timer clock and acts as a clock divider for the timer counter stage. The ratio can be managed
by accessing the ratio definition field of the control register (PTV and PRE of TCLR). See
The timer rate is defined by:
• The value of the prescaler fields (PRE and PTV of TCLR register)
• The value loaded into the Timer Load Register (TLDR).
The timer rate equation is as follows:
(FFFF FFFFh – TLDR + 1) × timer Clock period × Clock Divider (PS)
With timer Clock period = 1/ timer Clock frequency and PS = 2(PTV + 1).
As an example, if we consider a timer clock input of 32 kHz, with a PRE field equal to 0, the timer
output period is:
17.2.1.7 Dual Mode Timer Under Emulation
During emulation mode (when PINSUSPENDN signal is active), the timer can/cannot continue running
according to the value of the EmuFree bit of the timer OCP configuration register (TIOCP_CFG).
If EmuFree is 1, timer execution is not stopped and, regardless of the value of PINSUSPENDN signal,
and the interrupt assertion is still generated when overflow is reached.
If EmuFree is 0, counters (prescaler/timer) are frozen and an increment start occurs again as soon as
PINSUSPENDN becomes inactive. The asynchronous input pin is internally synchronized on 2 TIMER
clock rising edges.
1640
Timers
Preliminary
Table 17-3. Prescaler Clock Ratios Value
PRE
0
1
1
1
1
1
1
1
1
Table 17-4. Value and Corresponding Interrupt
Period
TLDR
0000 0000h
FFFF 0000h
FFFF FFF0h
FFFF FFFEh
© 2011, Texas Instruments Incorporated
PTV Divisor (PS)
X 1
0 2
1 4
2 8
3 16
4 32
5 64
6 128
7 256
Interrupt period
37 h
2 s
500 us
62.5 us
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Table 17-3.
SPRUGX9 – 15 April 2011
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