Mcbsp_Rcerc_Reg; Mcbsp_Rcerd_Reg - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
Table of Contents

Advertisement

Registers
11.3.18 McBSP Receive Channel Enable Register Partition C (RCERC_REG)
The McBSP_RCERC_REG register is shown in
31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-16
Reserved
15-0
RCERC
11.3.19 McBSP Receive Channel Enable Register Partition D (RCERD_REG)
The McBSP_RCERD_REG register is shown in
31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-16
Reserved
15-0
RCERD
1194
Multichannel Buffered Serial Port (McBSP)
Preliminary
Figure 11-50. McBSP_RCERC_REG
R-0
Table 11-37. McBSP_RCERC_REG Field Descriptions
Value
Description
0
Reserved.
0
Receive Channel Enable.
RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C.
RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C.
Figure 11-51. McBSP_RCERD_REG
R-0
Table 11-38. McBSP_RCERD_REG Field Descriptions
Value
Description
0
Reserved.
0
Receive Channel Enable.
RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D.
RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D.
© 2011, Texas Instruments Incorporated
Figure 11-50
and described in
16 15
Figure 11-51
and described in
16 15
www.ti.com
Table
11-37.
RCERC
R/W-0
Table
11-38.
RCERD
R/W-0
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
0
0

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the TMS320C6A816 Series and is the answer not in the manual?

Table of Contents