Link_Ctrl Register; Link_Ctrl Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
13.4.12.5 PL_LINK_CTRL Register
31
15
Reserved
7 6
FLNK_MODE Reserved
R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-22 Reserved
21-16 LNK_MODE
15-12 Reserved
11-8 LNK_RATE
7 FLNK_MODE
6 Reserved
5 DLL_EN
4 Reserved
3 RST_ASRT
2 LPBK_EN
1 SCRM_DIS
0 OMSG_REQ
1388
Peripheral Component Interconnect Express (PCIe)
Preliminary
Figure 13-141. PL_LINK_CTRL Register
Reserved
R-0
12
R-0
5 4
DLL_EN Reserved
R/W-1 R-0
Table 13-152. PL_LINK_CTRL Register Field Descriptions
Value Description
0 Reserved
0-3Fh Link Mode Enable.
0 Reserved
1h ×1
2h Reserved
3h ×2
4h-6h Reserved
7h ×4
8h-Eh Reserved
Fh ×8
10h-1Eh Reserved
1Fh ×16
20h-3Eh Reserved
3Fh ×32
0 Reserved
0-Fh Default Link Rate. For 2.5, it is 1h. This register does not affect any functionality.
0 Fast Link Mode
0 Reserved
1 DLL Link Enable
0 Reserved
0 Reset Assert
0 Loopback Enable
0 Scramble Disable
0 Other Message Request
© 2011, Texas Instruments Incorporated
22 21
11
LNK_RATE
R/W-1
3 2
RST_ASRT LPBK_EN
R/W-0 R/W-0
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16
LNK_MODE
R/W-3h
8
1 0
SCRM_DIS OMSG_REQ
R/W-0 R/W-0
SPRUGX9 – 15 April 2011
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