Mcbsp_Pcr_Reg Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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Table 11-36. McBSP_PCR_REG Field Descriptions (continued)
Bit Field
8 CLKRM
7 SCLKME
6 CLKS_STAT
5 DX_STAT
4 DR_STAT
3 FSXP
2 FSRP
1 CLKXP
0 CLKRP
SPRUGX9 – 15 April 2011
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Preliminary
Value Description
Receiver Clock Mode.
0 Case 1: Digital loop back mode not set (DLB=0) in SPCR1:
Receive clock (CLKR) is an input driven by an external clock.
Case 2: Digital loop back mode set (DLB=1) in SPCR1:
Receive clock (not the CLKR pin) is driven by transmit clock (CLKX), which is based on the CLKXM
bit in the PCR. CLKR pin is in high-impedance.
1 Case 1: Digital loop back mode not set (DLB=0) in SPCR1:
CLKR is an output pin and is driven by the internal sample rate generator.
Case 2: Digital loop back mode set (DLB=1) in SPCR1:
CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based on
the CLKRM bit in the PCR.
SCLKME Sample rate generator input clock mode bit 0
The sample rate generator can produce a clock signal, CLKG. The frequency of CLKG is:
CLKG frequency = (Input clock frequency) / (CLKGDV + 1)
SCLKME is used in conjunction with the CLKSM bit to select the input clock:
0 CLKSM = 0: Signal on CLKS pin.
CLKSM = 1: McBSP_OCP clock.
1 CLKSM = 0: Signal on CLKR pin.
CLKSM = 1: Signal on CLKX pin.
CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy)
0 The signal on the CLKS pin is low.
1 The signal on the CLKS pin is high.
DX pin status. Reflects value driven on to DX pin when selected as a general purpose output.
(legacy)
0 Drive the signal on the DX pin low.
1 Drive the signal on the DX pin high.
DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy)
0 The signal on DR pin is low.
1 The signal on DR pin is high.
Transmit Frame-Synchronization Polarity.
0 Frame-synchronization pulse FSX is active high.
1 Frame-synchronization pulse FSX is active low.
Receive Frame-Synchronization Polarity.
0 Frame-synchronization pulse FSR is active high.
1 Frame-synchronization pulse FSR is active low.
Transmit Clock Polarity.
0 Transmit data driven on rising edge of CLKX.
1 Transmit data driven on falling edge of CLKX.
Receive Clock Polarity.
0 Receive data sampled on falling edge of CLKR.
1 Receive data sampled on rising edge of CLKR.
© 2011, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Registers
1193