Table of Contents
Advertisement
www.ti.com
14.7.4.28 CM_TIMER4_CLKSEL Register
The CM_TIMER4_CLKSEL register selects the Mux select line for TIMER4 clock. It is shown and
described in the figure and table below
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-2
Reserved
1-0
CLKSEL
14.7.4.29 CM_TIMER5_CLKSEL Register
The CM_TIMER5_CLKSEL register selects the Mux select line for TIMER5 clock. It is shown and
described in the figure and table below
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-2
Reserved
1-0
CLKSEL
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Figure 14-45. CM_TIMER4_CLKSEL Register
Reserved
R-0
Table 14-60. CM_TIMER4_CLKSEL Register Field Descriptions
Value
Description
0
Reserved
Selects the Mux select line for TIMER4 clock [warm reset insensitive]
0
Select TIMER clock to be TCLKIN
1h
Select TIMER clock to be external 32 KHz clock.(After MUX)
2h
Select TIMER clock to be CLKIN
3h
Reserved
Figure 14-46. CM_TIMER5_CLKSEL Register
Reserved
R-0
Table 14-61. CM_TIMER5_CLKSEL Register Field Descriptions
Value
Description
0
Reserved
Selects the Mux select line for TIMER5 clock [warm reset insensitive]
0
Select TIMER clock to be TCLKIN
1h
Select TIMER clock to be external 32 KHz clock.(After MUX)
2h
Select TIMER clock to be CLKIN
3h
Reserved
© 2011, Texas Instruments Incorporated
Power, Reset, and Clock Management (PRCM) Module
Registers
2
1
0
CLKSEL
R/W-1
2
1
0
CLKSEL
R/W-1
1445
Advertisement
Table of Contents
