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10.3.4 Pin Data Output Register (PDOUT)
The pin data output register (PDOUT) holds a value for data out at all times, and may be read back at
all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However, the data
value in PDOUT is driven out onto the McASP pin only if the corresponding bit in PFUNC is set to 1
(GPIO function) and the corresponding bit in PDIR is set to 1 (output). When reading data, returns the
corresponding bit value in PDOUT[n], does not return input from I/O pin; when writing data, writes to the
corresponding PDOUT[n] bit. The PDOUT is shown in
PDOUT has these aliases or alternate addresses:
•
PDSET - when written to at this address, writing a 1 to a bit in PDSET sets the corresponding bit in
PDOUT to 1; writing a 0 has no effect and keeps the bits in PDOUT unchanged.
•
PDCLR - when written to at this address, writing a 1 to a bit in PDCLR clears the corresponding bit
in PDOUT to 0; writing a 0 has no effect and keeps the bits in PDOUT unchanged.
There is only one set of data out bits, PDOUT[31-0]. The other registers, PDSET and PDCLR, are just
different addresses for the same control bits, with different behaviors during writes.
Writing to Reserved Bits
Writing a value other than 0 to reserved bits in this register may cause
improper device operation.
31
30
AFSR
AHCLKR
R/W-0
R/W-0
23
7
6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUGX9 – 15 April 2011
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Preliminary
CAUTION
Figure 10-41. Pin Data Output Register (PDOUT)
29
28
ACLKR
AFSX
R/W-0
R/W-0
Reserved
R-0
5
4
AXR5
AXR4
R/W-0
R/W-0
© 2011, Texas Instruments Incorporated
Figure 10-41
and described in
27
26
AHCLKX
ACLKX
R/W-0
R/W-0
3
2
AXR3
AXR2
R/W-0
R/W-0
Multichannel Audio Serial Port (McASP)
Registers
Table
10-13.
25
24
AMUTE
Reserved
R/W-0
R-0
8
1
0
AXR1
AXR0
R/W-0
R/W-0
1075
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