I2C Data Transfer Formats - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Architecture
The least significant R/nW of the address byte indicates the direction of transmission of the following
data bytes. If R/nW is 0, the master writes data into the selected slave; if it is 1, the master reads data
out of the slave.
1
7
S Slave address
7-Bit Addressing Format
1
7
S 1 1 1 1 0 A A
A A = 2 MSBs
10-Bit Addressing Format
1
7
S Slave address
1
7-Bit Addressing Format With Repeated START Condition
7.2.5.2 Master Transmitter
In this mode, data assembled in one of the previously described data formats is shifted out on the serial
data line SDA in synch with the self-generated clock pulses on the serial clock line SCL. The clock
pulses are inhibited and SCL held low when the intervention of the processor is required (XUDF) after a
byte has been transmitted.
7.2.5.3 Master Receiver
This mode can only be entered from the master transmitter mode. With either of the address formats
(Figure 6 (a), (b), and (c)), the master receiver is entered after the slave address byte and bit R/W_ has
been transmitted, if R/W_ is high. Serial data bits received on bus line SDA are shifted in synch with the
self-generated clock pulses on SCL. The clock pulses are inhibited and SCL held low when the
intervention of the processor is required (ROVR) after a byte has been transmitted. At the end of a
transfer, it generates the stop condition.
7.2.5.4 Slave Transmitter
This mode can only be entered from the slave receiver mode. With either of the address formats
(Figure 6 (a), (b), and (c)), the slave transmitter is entered if the slave address byte is the same as its
own address and bit R/W_ has been transmitted, if R/W_ is high. The slave transmitter shifts the serial
data out on the data line SDA in synch with the clock pulses that are generated by the master device. It
does not generate the clock but it can hold clock line SCL low while intervention of the CPU is required
(XUDF).
7.2.5.5 Slave Receiver
In this mode, serial data bits received on the bus line SDA are shifted-in in synch with the clock pulses
on SCL that are generated by the master device. It does not generate the clock but it can hold clock
line SCL low while intervention of the CPU is required (ROVR) following the reception of a byte.
850
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Figure 7-6. I2C Data Transfer Formats
1 1
R/W ACK
1 1
0 ACK A A A A A A A A
R/W 8 LSBs of slave address
1 1 1 1
n
R/W ACK Data ACK S
Any
number
© 2011, Texas Instruments Incorporated
1
n
Data ACK
1
8
ACK
1 1
7
Slave address R/W ACK
1
www.ti.com
1 1
n
Data ACK P
1 1
n
Data ACK P
1 1
n
Data ACK P
Any number
SPRUGX9 – 15 April 2011
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