Pm_Active_Pwrstctrl Register; Pm_Active_Pwrstctrl Register Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
14.7.8 PRM_ACTIVE Device

14.7.8.1 PM_ACTIVE_PWRSTCTRL Register

This register controls the ACTIVE power state to reach upon a domain sleep transition [warm reset
insensitive]. It is shown and described in the figure and table below.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-84. PM_ACTIVE_PWRSTCTRL Register Field Descriptions
Bit Field
31-18 Reserved
17-16 ACTIVE_MEM_ONSTATE
15-2 Reserved
1-0 POWERSTATE
1468
Power, Reset, and Clock Management (PRCM) Module
Preliminary
Figure 14-69. PM_ACTIVE_PWRSTCTRL Register
Reserved
R-0
Reserved
R-0
Value Description
0 Reserved
Active domain memory state when domain is ON
0 Reserved
1h Reserved
2h Reserved
3h Memory bank is on when the domain is ON
0 Reserved
Power state control
0 OFF State [warm reset insensitive]
1h Reserved
2h Reserved
3h ON State [warm reset insensitive]
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18 17
ACTIVE_MEM_ONSTATE
R-3h
2 1
POWERSTATE
R/W-0
SPRUGX9 – 15 April 2011
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16
0